[llvm] r365507 - [mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 9 08:48:06 PDT 2019
Author: atanasyan
Date: Tue Jul 9 08:48:05 2019
New Revision: 365507
URL: http://llvm.org/viewvc/llvm-project?rev=365507&view=rev
Log:
[mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC
Support for 64-bit coprocessors on a 32-bit architecture
was added in `MIPS32 R2`.
Modified:
llvm/trunk/test/CodeGen/Mips/abiflags32.ll
llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll
llvm/trunk/test/CodeGen/Mips/cconv/return-hard-float.ll
llvm/trunk/test/CodeGen/Mips/cfi_offset.ll
llvm/trunk/test/CodeGen/Mips/fp-contract.ll
llvm/trunk/test/CodeGen/Mips/fp64a.ll
llvm/trunk/test/CodeGen/Mips/msa/2r.ll
llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll
llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll
llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll
llvm/trunk/test/CodeGen/Mips/msa/arithmetic.ll
llvm/trunk/test/CodeGen/Mips/msa/arithmetic_float.ll
llvm/trunk/test/CodeGen/Mips/msa/basic_operations_float.ll
llvm/trunk/test/CodeGen/Mips/msa/bit.ll
llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll
llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll
llvm/trunk/test/CodeGen/Mips/msa/bmzi_bmnzi.ll
llvm/trunk/test/CodeGen/Mips/msa/compare.ll
llvm/trunk/test/CodeGen/Mips/msa/compare_float.ll
llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll
llvm/trunk/test/CodeGen/Mips/msa/elm_cxcmsa.ll
llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll
llvm/trunk/test/CodeGen/Mips/msa/elm_move.ll
llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll
llvm/trunk/test/CodeGen/Mips/msa/endian.ll
llvm/trunk/test/CodeGen/Mips/msa/frameindex.ll
llvm/trunk/test/CodeGen/Mips/msa/i10.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll
llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll
llvm/trunk/test/CodeGen/Mips/msa/i8.ll
llvm/trunk/test/CodeGen/Mips/msa/immediates-bad.ll
llvm/trunk/test/CodeGen/Mips/msa/immediates.ll
llvm/trunk/test/CodeGen/Mips/msa/inline-asm.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll
llvm/trunk/test/CodeGen/Mips/msa/shift-dagcombine.ll
llvm/trunk/test/CodeGen/Mips/msa/shift_constant_pool.ll
llvm/trunk/test/CodeGen/Mips/msa/shift_no_and.ll
llvm/trunk/test/CodeGen/Mips/msa/shuffle.ll
llvm/trunk/test/CodeGen/Mips/msa/special.ll
llvm/trunk/test/CodeGen/Mips/msa/spill.ll
llvm/trunk/test/CodeGen/Mips/msa/vec.ll
llvm/trunk/test/CodeGen/Mips/msa/vecs10.ll
llvm/trunk/test/CodeGen/Mips/stack-alignment.ll
Modified: llvm/trunk/test/CodeGen/Mips/abiflags32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/abiflags32.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/abiflags32.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/abiflags32.ll Tue Jul 9 08:48:05 2019
@@ -1,6 +1,9 @@
-; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 %s -o - | FileCheck %s
-; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -mattr=fp64 %s -o - | FileCheck -check-prefix=CHECK-64 %s
-; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips64 -target-abi n32 %s -o - | FileCheck -check-prefix=CHECK-64n %s
+; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux \
+; RUN: -mcpu=mips32 %s -o - | FileCheck %s
+; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux \
+; RUN: -mcpu=mips32r2 -mattr=fp64 %s -o - | FileCheck -check-prefix=CHECK-64 %s
+; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux \
+; RUN: -mcpu=mips64 -target-abi n32 %s -o - | FileCheck -check-prefix=CHECK-64n %s
; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 \
; RUN: -mattr=soft-float %s -o - | FileCheck -check-prefix=SOFT %s
; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32r6 \
Modified: llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll Tue Jul 9 08:48:05 2019
@@ -1,5 +1,7 @@
-; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=O32-FP64-INV %s
-; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=O32-FP64-INV %s
+; RUN: llc -march=mips -mattr=+o32,+fp64,+mips32r2 < %s \
+; RUN: | FileCheck --check-prefix=O32-FP64-INV %s
+; RUN: llc -march=mipsel -mattr=+o32,+fp64,+mips32r2 < %s \
+; RUN: | FileCheck --check-prefix=O32-FP64-INV %s
; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
Modified: llvm/trunk/test/CodeGen/Mips/cconv/return-hard-float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/return-hard-float.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cconv/return-hard-float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cconv/return-hard-float.ll Tue Jul 9 08:48:05 2019
@@ -1,17 +1,27 @@
-; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s \
+; RUN: | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s \
+; RUN: | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s \
+; RUN-TODO: | FileCheck --check-prefixes=ALL,O32 %s
+; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s \
+; RUN-TODO: | FileCheck --check-prefixes=ALL,O32 %s
-; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
-; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
+; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s \
+; RUN: | FileCheck --check-prefixes=ALL,N32 %s
+; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s \
+; RUN: | FileCheck --check-prefixes=ALL,N32 %s
-; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
-; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
+; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s \
+; RUN: | FileCheck --check-prefixes=ALL,N64 %s
+; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s \
+; RUN: | FileCheck --check-prefixes=ALL,N64 %s
-; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefixes=ALL,032FP64 %s
-; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefixes=ALL,032FP64 %s
+; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static -mattr=+o32,+fp64,+mips32r2 < %s \
+; RUN: | FileCheck --check-prefixes=ALL,032FP64 %s
+; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static -mattr=+o32,+fp64,+mips32r2 < %s \
+; RUN: | FileCheck --check-prefixes=ALL,032FP64 %s
; Test the float returns for all ABI's and byte orders as specified by
; section 5 of MD00305 (MIPS ABIs Described).
Modified: llvm/trunk/test/CodeGen/Mips/cfi_offset.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cfi_offset.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cfi_offset.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cfi_offset.ll Tue Jul 9 08:48:05 2019
@@ -2,8 +2,8 @@
; RUN: llc -march=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
-; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
-; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
+; RUN: llc -march=mips -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
+; RUN: llc -march=mipsel -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
@var = global double 0.0
Modified: llvm/trunk/test/CodeGen/Mips/fp-contract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fp-contract.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fp-contract.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fp-contract.ll Tue Jul 9 08:48:05 2019
@@ -1,9 +1,12 @@
; Test that the compiled does not fuse fmul and fadd into fmadd when no -fp-contract=fast
; option is set (the same applies for fmul, fsub and fmsub).
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -fp-contract=off < %s | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF
-; RUN: llc -march=mips -mattr=+msa,+fp64 -fp-contract=fast < %s | FileCheck %s --check-prefixes=CHECK-CONTRACT-FAST
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -fp-contract=off < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -fp-contract=fast < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK-CONTRACT-FAST
declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>)
declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>)
Modified: llvm/trunk/test/CodeGen/Mips/fp64a.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fp64a.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fp64a.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fp64a.ll Tue Jul 9 08:48:05 2019
@@ -7,9 +7,7 @@
; We don't test MIPS32r1 since support for 64-bit coprocessors (such as a 64-bit
; FPU) on a 32-bit architecture was added in MIPS32r2.
; FIXME: We currently don't test that attempting to use FP64 on MIPS32r1 is an
-; error either. This is because a large number of CodeGen tests are
-; incorrectly using this case. We should fix those test cases then add
-; this check here.
+; error either.
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-BE
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A
Modified: llvm/trunk/test/CodeGen/Mips/msa/2r.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2r.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2r.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2r.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 2R instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_nloc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_nloc_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll Tue Jul 9 08:48:05 2019
@@ -1,9 +1,9 @@
; Test the MSA intrinsics that are encoded with the 2R instruction format and
; convert scalars to vectors.
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 2RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_flog2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_flog2_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA floating point conversion intrinsics (e.g. float->double) that
; are encoded with the 2RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_fexupl_w_ARG1 = global <8 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00, half 5.000000e+00, half 6.000000e+00, half 7.000000e+00>, align 16
@llvm_mips_fexupl_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA integer to floating point conversion intrinsics that are encoded
; with the 2RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
@llvm_mips_ffint_s_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA fixed-point to floating point conversion intrinsics that are
; encoded with the 2RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_ffql_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll Tue Jul 9 08:48:05 2019
@@ -2,8 +2,8 @@
; 2RF instruction format. This includes conversions but other instructions such
; as fclass are also here.
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fclass_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA floating-point to fixed-point conversion intrinsics that are
; encoded with the 2RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_ftq_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_ftq_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'a'
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
; It should fail to compile without fp64.
; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'b'
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'c'
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_ceq_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ceq_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'd'
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_div_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_div_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'i'
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_ilvev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ilvev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'm'
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_max_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_max_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'p'
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_pckev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_pckev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 's'
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_sld_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'v'
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_vshf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_vshf_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format and
; use the result as a third operand.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_maddv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_maddv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll Tue Jul 9 08:48:05 2019
@@ -2,8 +2,8 @@
; use the result as a third operand and results in wider elements than the
; operands had.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_dpadd_s_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16
@llvm_mips_dpadd_s_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format and
; use the result as a third operand.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_fmadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fmadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format and
; use the result as a third operand and perform fixed-point operations.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_madd_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA floating-point conversion intrinsics that are encoded with the
; 3RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fexdo_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format and
; take an integer as an operand.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_fexp2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fexp2_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format and
; produce an integer as a result.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_fcaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fcaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction
; format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_mul_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/arithmetic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/arithmetic.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/arithmetic.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/arithmetic.ll Tue Jul 9 08:48:05 2019
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=ALL,MIPS
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPS
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL
define void @add_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; ALL-LABEL: add_v16i8:
Modified: llvm/trunk/test/CodeGen/Mips/msa/arithmetic_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/arithmetic_float.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/arithmetic_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/arithmetic_float.ll Tue Jul 9 08:48:05 2019
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
define void @add_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
; CHECK: add_v4f32:
Modified: llvm/trunk/test/CodeGen/Mips/msa/basic_operations_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/basic_operations_float.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/basic_operations_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/basic_operations_float.ll Tue Jul 9 08:48:05 2019
@@ -1,9 +1,15 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,O32 %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,O32 %s
-; RUN: llc -march=mips64 -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64el -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,N64 %s
-; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,N64 %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
+; RUN: | FileCheck -check-prefixes=ALL,O32 %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
+; RUN: | FileCheck -check-prefixes=ALL,O32 %s
+; RUN: llc -march=mips64 -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \
+; RUN: | FileCheck -check-prefixes=ALL,N32 %s
+; RUN: llc -march=mips64el -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \
+; RUN: | FileCheck -check-prefixes=ALL,N32 %s
+; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \
+; RUN: | FileCheck -check-prefixes=ALL,N64 %s
+; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \
+; RUN: | FileCheck -check-prefixes=ALL,N64 %s
@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
@v2f64 = global <2 x double> <double 0.0, double 0.0>
Modified: llvm/trunk/test/CodeGen/Mips/msa/bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/bit.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/bit.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/bit.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the BIT instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_sat_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_sat_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; Test the bitcast operation for big-endian and little-endian.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=BIGENDIAN %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=LITENDIAN %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s
define void @v16i8_to_v16i8(<16 x i8>* %src, <16 x i8>* %dst) nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll Tue Jul 9 08:48:05 2019
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
define void @and_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: and_v16i8:
Modified: llvm/trunk/test/CodeGen/Mips/msa/bmzi_bmnzi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/bmzi_bmnzi.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/bmzi_bmnzi.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/bmzi_bmnzi.ll Tue Jul 9 08:48:05 2019
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, align 16
@llvm_mips_bmnzi_b_ARG2 = global <16 x i8> zeroinitializer, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/compare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/compare.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/compare.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/compare.ll Tue Jul 9 08:48:05 2019
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
define void @ceq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: ceq_v16i8:
Modified: llvm/trunk/test/CodeGen/Mips/msa/compare_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/compare_float.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/compare_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/compare_float.ll Tue Jul 9 08:48:05 2019
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind
declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind
Modified: llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll Tue Jul 9 08:48:05 2019
@@ -1,9 +1,9 @@
; Test the MSA intrinsics that are encoded with the ELM instruction format and
; are element extraction operations.
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64
Modified: llvm/trunk/test/CodeGen/Mips/msa/elm_cxcmsa.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/elm_cxcmsa.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/elm_cxcmsa.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/elm_cxcmsa.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM
; instruction format).
-; RUN: llc -march=mips -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s
define i32 @msa_ir_cfcmsa_test() nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll Tue Jul 9 08:48:05 2019
@@ -1,9 +1,9 @@
; Test the MSA element insertion intrinsics that are encoded with the ELM
; instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64
Modified: llvm/trunk/test/CodeGen/Mips/msa/elm_move.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/elm_move.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/elm_move.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/elm_move.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA move intrinsics (which are encoded with the ELM instruction
; format).
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_move_vb_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_move_vb_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the ELM instruction format and
; are either shifts or slides.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_sldi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_sldi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/endian.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/endian.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/endian.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/endian.ll Tue Jul 9 08:48:05 2019
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=BIGENDIAN %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=LITENDIAN %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s
@v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
@v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
Modified: llvm/trunk/test/CodeGen/Mips/msa/frameindex.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/frameindex.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/frameindex.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/frameindex.ll Tue Jul 9 08:48:05 2019
@@ -1,5 +1,7 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefixes=MIPS32-AE,MIPS32-BE %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefixes=MIPS32-AE,MIPS32-LE %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s \
+; RUN: | FileCheck -check-prefixes=MIPS32-AE,MIPS32-BE %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s \
+; RUN: | FileCheck -check-prefixes=MIPS32-AE,MIPS32-LE %s
define void @loadstore_v16i8_near() nounwind {
; MIPS32-AE: loadstore_v16i8_near:
Modified: llvm/trunk/test/CodeGen/Mips/msa/i10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i10.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i10.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i10.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the I10 instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_bnz_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'a'
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_addvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_addvi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'b'
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bclri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'c'
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_ceqi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ceqi_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'm'
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_maxi_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_maxi_s_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll Tue Jul 9 08:48:05 2019
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=ALL,MIPS
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s \
+; RUN: | FileCheck %s --check-prefixes=ALL,MIPS
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s \
+; RUN: | FileCheck %s --check-prefixes=ALL,MIPSEL
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 's'
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format and
; are loads or stores.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_ld_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i8.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i8.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i8.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the I8 instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/immediates-bad.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/immediates-bad.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/immediates-bad.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/immediates-bad.ll Tue Jul 9 08:48:05 2019
@@ -1,4 +1,4 @@
-; RUN: not llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s 2> %t1
+; RUN: not llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s 2> %t1
; RUN: FileCheck %s < %t1
; Test that the immediate intrinsics with out of range values trigger an error.
Modified: llvm/trunk/test/CodeGen/Mips/msa/immediates.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/immediates.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/immediates.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/immediates.ll Tue Jul 9 08:48:05 2019
@@ -1,4 +1,5 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,MSA32
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
+; RUN: | FileCheck %s -check-prefixes=CHECK,MSA32
; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n32 < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,MSA64,MSA64N32
; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n64 < %s \
Modified: llvm/trunk/test/CodeGen/Mips/msa/inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/inline-asm.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/inline-asm.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/inline-asm.ll Tue Jul 9 08:48:05 2019
@@ -1,6 +1,6 @@
; A basic inline assembly test
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@v4i32_r = global <4 x i32> zeroinitializer, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a
; "Unexpected illegal type!" assertion.
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a
; `Opc && "Cannot copy registers"' assertion.
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a "Cannot select ..." error.
; This was because undef's are ignored when checking if a vector constant is a
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a "Cannot select ..." error.
; This happened because the legalizer treated undef's in the <4 x float>
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA after dereferencing a null this pointer.
; It should at least successfully build.
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a
; "Don't know how to expand this condition!" unreachable.
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a
; "Type for zero vector elements is not legal" assertion.
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed to select instructions for extract_vector_elt for
; v4f32 on MSA.
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test is based on an llvm-stress generated test case with seed=449609655
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a
; `Num < NumOperands && "Invalid child # of SDNode!"' assertion.
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed to select instructions for extract_vector_elt for
; v2f64 on MSA.
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed to select code for a truncstore of a
; build_vector.
Modified: llvm/trunk/test/CodeGen/Mips/msa/shift-dagcombine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/shift-dagcombine.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/shift-dagcombine.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/shift-dagcombine.ll Tue Jul 9 08:48:05 2019
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
define void @ashr_v4i32(<4 x i32>* %c) nounwind {
; CHECK-LABEL: ashr_v4i32:
Modified: llvm/trunk/test/CodeGen/Mips/msa/shift_constant_pool.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/shift_constant_pool.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/shift_constant_pool.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/shift_constant_pool.ll Tue Jul 9 08:48:05 2019
@@ -1,10 +1,14 @@
; Test whether the following functions, with vectors featuring negative or values larger than the element
; bit size have their results of operations generated correctly when placed into constant pools
-; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64 %s
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32 %s
-; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64 %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32 %s
+; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \
+; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
+; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s
+; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \
+; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,mips32r2 -relocation-model=pic < %s \
+; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s
@llvm_mips_bclr_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/shift_no_and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/shift_no_and.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/shift_no_and.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/shift_no_and.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; Test the absence of the andi.b / and.v instructions
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/shuffle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/shuffle.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/shuffle.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/shuffle.ll Tue Jul 9 08:48:05 2019
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
define void @vshf_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK-LABEL: vshf_v16i8_0:
Modified: llvm/trunk/test/CodeGen/Mips/msa/special.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/special.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/special.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/special.ll Tue Jul 9 08:48:05 2019
@@ -1,6 +1,6 @@
; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS32
; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS64
Modified: llvm/trunk/test/CodeGen/Mips/msa/spill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/spill.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/spill.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/spill.ll Tue Jul 9 08:48:05 2019
@@ -1,8 +1,8 @@
; Test that the correct instruction is chosen for spill and reload by trying
; to have 33 live MSA registers simultaneously
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
define i32 @test_i8(<16 x i8>* %p0, <16 x i8>* %q1) nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/Mips/msa/vec.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/vec.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/vec.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/vec.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,9 @@
; Test the MSA intrinsics that are encoded with the VEC instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefix=ANYENDIAN %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefix=ANYENDIAN %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
+; RUN: | FileCheck -check-prefix=ANYENDIAN %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
+; RUN: | FileCheck -check-prefix=ANYENDIAN %s
@llvm_mips_and_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_and_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/vecs10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/vecs10.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/vecs10.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/vecs10.ll Tue Jul 9 08:48:05 2019
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the VECS10 instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_bnz_v_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/stack-alignment.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/stack-alignment.ll?rev=365507&r1=365506&r2=365507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/stack-alignment.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/stack-alignment.ll Tue Jul 9 08:48:05 2019
@@ -1,6 +1,6 @@
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
; RUN: llc -march=mipsel -stack-alignment=32 < %s | FileCheck %s -check-prefix=A32-32
-; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=32
+; RUN: llc -march=mipsel -mattr=+fp64,+mips32r2 < %s | FileCheck %s -check-prefix=32
; RUN: llc -march=mips64el -mcpu=mips3 < %s | FileCheck %s -check-prefix=64
; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
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