[llvm] r365484 - AMDGPU/GlobalISel: Select G_SUB
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 9 07:05:11 PDT 2019
Author: arsenm
Date: Tue Jul 9 07:05:11 2019
New Revision: 365484
URL: http://llvm.org/viewvc/llvm-project?rev=365484&view=rev
Log:
AMDGPU/GlobalISel: Select G_SUB
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp?rev=365484&r1=365483&r2=365484&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp Tue Jul 9 07:05:11 2019
@@ -212,7 +212,7 @@ static int64_t getConstant(const Machine
return MI->getOperand(1).getCImm()->getSExtValue();
}
-bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const {
+bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const {
MachineBasicBlock *BB = I.getParent();
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
@@ -221,11 +221,13 @@ bool AMDGPUInstructionSelector::selectG_
unsigned Size = RBI.getSizeInBits(DstReg, MRI, TRI);
const RegisterBank *DstRB = RBI.getRegBank(DstReg, MRI, TRI);
const bool IsSALU = DstRB->getID() == AMDGPU::SGPRRegBankID;
+ const bool Sub = I.getOpcode() == TargetOpcode::G_SUB;
if (Size == 32) {
if (IsSALU) {
+ const unsigned Opc = Sub ? AMDGPU::S_SUB_U32 : AMDGPU::S_ADD_U32;
MachineInstr *Add =
- BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstReg)
+ BuildMI(*BB, &I, DL, TII.get(Opc), DstReg)
.add(I.getOperand(1))
.add(I.getOperand(2));
I.eraseFromParent();
@@ -233,15 +235,18 @@ bool AMDGPUInstructionSelector::selectG_
}
if (STI.hasAddNoCarry()) {
- I.setDesc(TII.get(AMDGPU::V_ADD_U32_e64));
+ const unsigned Opc = Sub ? AMDGPU::V_SUB_U32_e64 : AMDGPU::V_ADD_U32_e64;
+ I.setDesc(TII.get(Opc));
I.addOperand(*MF, MachineOperand::CreateImm(0));
I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
+ const unsigned Opc = Sub ? AMDGPU::V_SUB_I32_e64 : AMDGPU::V_ADD_I32_e64;
+
Register UnusedCarry = MRI.createVirtualRegister(TRI.getWaveMaskRegClass());
MachineInstr *Add
- = BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADD_I32_e64), DstReg)
+ = BuildMI(*BB, &I, DL, TII.get(Opc), DstReg)
.addDef(UnusedCarry, RegState::Dead)
.add(I.getOperand(1))
.add(I.getOperand(2))
@@ -250,6 +255,8 @@ bool AMDGPUInstructionSelector::selectG_
return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI);
}
+ assert(!Sub && "illegal sub should not reach here");
+
const TargetRegisterClass &RC
= IsSALU ? AMDGPU::SReg_64_XEXECRegClass : AMDGPU::VReg_64RegClass;
const TargetRegisterClass &HalfRC
@@ -408,7 +415,7 @@ bool AMDGPUInstructionSelector::selectG_
}
bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const {
- return selectG_ADD(I);
+ return selectG_ADD_SUB(I);
}
bool AMDGPUInstructionSelector::selectG_IMPLICIT_DEF(MachineInstr &I) const {
@@ -1213,7 +1220,8 @@ bool AMDGPUInstructionSelector::select(M
switch (I.getOpcode()) {
case TargetOpcode::G_ADD:
- if (selectG_ADD(I))
+ case TargetOpcode::G_SUB:
+ if (selectG_ADD_SUB(I))
return true;
LLVM_FALLTHROUGH;
default:
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h?rev=365484&r1=365483&r2=365484&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h Tue Jul 9 07:05:11 2019
@@ -73,7 +73,7 @@ private:
bool selectG_TRUNC(MachineInstr &I) const;
bool selectG_SZA_EXT(MachineInstr &I) const;
bool selectG_CONSTANT(MachineInstr &I) const;
- bool selectG_ADD(MachineInstr &I) const;
+ bool selectG_ADD_SUB(MachineInstr &I) const;
bool selectG_EXTRACT(MachineInstr &I) const;
bool selectG_MERGE_VALUES(MachineInstr &I) const;
bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir?rev=365484&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir Tue Jul 9 07:05:11 2019
@@ -0,0 +1,61 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
+
+---
+name: sub_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
+
+
+ ; GFX6-LABEL: name: sub_s32
+ ; GFX6: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
+ ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
+ ; GFX6: [[S_SUB_U32_:%[0-9]+]]:sreg_32_xm0 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_SUB_I32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec
+ ; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_SUB_I32_e64 [[S_SUB_U32_]], %7, 0, implicit $exec
+ ; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_SUB_I32_e64 %8, [[COPY2]], 0, implicit $exec
+ ; GFX6: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
+ ; GFX9-LABEL: name: sub_s32
+ ; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
+ ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
+ ; GFX9: [[S_SUB_U32_:%[0-9]+]]:sreg_32_xm0 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX9: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec
+ ; GFX9: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_U32_]], [[V_SUB_U32_e64_]], 0, implicit $exec
+ ; GFX9: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec
+ ; GFX9: FLAT_STORE_DWORD [[COPY3]], [[V_SUB_U32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s32) = COPY $sgpr1
+ %2:vgpr(s32) = COPY $vgpr0
+ %3:vgpr(p1) = COPY $vgpr3_vgpr4
+ %4:sgpr(s32) = G_CONSTANT i32 1
+ %5:sgpr(s32) = G_CONSTANT i32 4096
+
+ ; sub ss
+ %6:sgpr(s32) = G_SUB %0, %1
+
+ ; sub vs
+ %7:vgpr(s32) = G_SUB %2, %6
+
+ ; sub sv
+ %8:vgpr(s32) = G_SUB %6, %7
+
+ ; sub vv
+ %9:vgpr(s32) = G_SUB %8, %2
+
+ G_STORE %9, %3 :: (store 4, addrspace 1)
+
+...
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