[PATCH] D63669: [RISCV] Allow parsing dot '.' in assembly

[John LLVM via Phabricator via llvm-commits]

JohnLLVM added a comment.

> 1. The tests you've added should probably go with the other tests of the `j` instruction in `llvm/test/MC/RISCV/rvi-aliases-valid.s` (and should match the others in that file).

Done. I have left a single one in the non-alias file, which I have reworked to not use an alias: this way, we also have an encoding test.

> 2. Please add a test of `jalr %lo(.)` to `rv32i-valid.s`. This will test that `.` can go in more complex places, and is not an instruction alias.

These advances cases are not handles by this review (even `j .+4` does not work). I intend to look at it after this review; currently, I am not sure how to proceed.

> 3. Please add a test to `rv32i-aliases-invalid.s` to test something like `addi x1, .` which will show what happens if someone provides `.` as an immediate somewhere that doesn't make sense.

Done.


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  https://reviews.llvm.org/D63669/new/

https://reviews.llvm.org/D63669