[PATCH] D64212: [ARM] MVE Vector Shifts

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: t.p.northover, samparker, SjoerdMeijer, simon_tatham, ostannard.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

This is basic shifts for MVE. There are many shifts in MVE, but the ones handled here are:

- VSHL (imm)
- VSHRu (imm)
- VSHRs (imm)
- VSHL (vector)
- VSHL (register)

MVE, like NEON before it, doesn't have shift right by a vector (or register). We instead have to negate the amount and shift in the opposite direction. This means we have to convert any SHR's into a from of SHL (that is still signed or unsigned) with a negated condition and selecting from there. MVE still does have shifting by an immediate for SHL, ASR and LSR.

NEON was previously lowering the shifts into intrinsics and selecting on the intrinsic. I've converted that to a node shared between NEON and MVE which shifts left whilst still storing sign (ARMISD::VSHLs and ARMISD:VSHLu). SHL are arbitrarily selected to a ARMISD:VSHLu (without the negation). The existing VSHL, VSHRu and VSHRs nodes have been renamed to VSHLimm, VSHRuimm and VSHRimm (along with a number of others for consistency), and are now lowered in LowerShift too, which helps some neon tests.

I've also added patterns for register forms, which work well for shift lefts but will require an extra fold of neg(vdup(x)) -> vdup(neg(x)) to work for right shifts.


https://reviews.llvm.org/D64212

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/ARMInstrNEON.td
  llvm/test/CodeGen/ARM/vpadd.ll
  llvm/test/CodeGen/ARM/vuzp.ll
  llvm/test/CodeGen/Thumb2/mve-shifts.ll

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