[PATCH] D64145: [AMDGPU] Add the adjusted FP as a livein register.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir:12
+
+  attributes #0 = { nounwind "amdgpu-dispatch-ptr" "amdgpu-flat-work-group-size"="1,1024" "amdgpu-implicitarg-num-bytes"="48" "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="+16-bit-insts,+ci-insts,+dpp,+fp32-denormals,+fp64-fp16-denormals,+gfx8-insts,+gfx9-insts,+s-memrealtime" "unsafe-fp-math"="false" "use-soft-float"="false" }
+...
----------------
You can at least drop the attributes, and probably the whole IR section 


================
Comment at: llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir:25
+stack:           
+  - { id: 0, type: spill-slot, size: 4, alignment: 4 }
+  - { id: 1, type: spill-slot, size: 4, alignment: 4 }
----------------
Shouldn’t need so many stack objects?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64145/new/

https://reviews.llvm.org/D64145