[PATCH] D64160: [ARM] Favour PL/MI over GE/LT when possible

Wed Jul 3 14:42:58 PDT 2019

dmgreen added a comment.

Thanks for taking a look. The codesize changes here are minor, but present and consistently down. It was actually performance that I was looking for though, with this coming up on a couple of hot loops I was seeing.  They do something like if ((a-b) < 0) ... a few times which previously was leaving the extra cmp instructions in. The changes in long shift also look like they may be useful.

================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:4730
+    if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
+      ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
     return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
----------------
efriedma wrote:
> Do you not need to check for ARMCC::MI here?  Or do we avoid that somehow?
The vsel can only handle GE, GT, VS and EQ apparently. The code above tries to invert the conditions to get one of these legal codes. So I don't believe that will usually be generated, and if it is then choosing MI over LT won't make much of a difference.

Without this change, we only end up generating a "vmovpl.f32 s0, s1" instead of a "vselge.f32 s0, s1, s0" in the tests I've added, so it didn't seem much worse in either case. The vsel is presumably better in general though.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64160/new/

https://reviews.llvm.org/D64160