[PATCH] D61289: [globalisel] Add G_SEXT_INREG

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D61289#1568835 <https://reviews.llvm.org/D61289#1568835>, @dsanders wrote:

> In D61289#1568788 <https://reviews.llvm.org/D61289#1568788>, @arsenm wrote:
>
> > In D61289#1568751 <https://reviews.llvm.org/D61289#1568751>, @dsanders wrote:
> >
> > >
> >
> >
> > Do any targets allow both the position and width to be specified as registers?
> >
> > Both the offset and width can be registers on AMDGPU (for the SALU version they are both packed in one register)
>
>
> In that case we'd need all four combinations if we did it by opcode. It would probably be better to go the other route to achieve a bitfield extract. That has some nasty side effects to sort out (e.g. what happens to the type indices if one of the operands is an immediate) but it should be possible.
>
> I think we should land this patch while we think of that as it will be fairly simple to convert G_SEXT_INREG to the more flexible G_SFBE in future. It's just a matter of checking for the 0 immediate when looking for G_SEXT_INREG and adding it when we build a G_SBFE


I would rather have G_SBFE/G_UBFE that accept arbitrary registers, and a separate G_SEXT_INREG. I wouldn't get any benefit from additional static versions


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