[PATCH] D64090: [Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: spatel, RKSimon, efriedma, t.p.northover, hfinkel.
lebedev.ri added a project: LLVM.
Herald added subscribers: jsji, kbarton, kristof.beyls, javed.absar, nemanjai.

This is the backend part of PR42457 <https://bugs.llvm.org/show_bug.cgi?id=42457>.
In middle-end, we'd want to prefer the form with two adds - D63992 <https://reviews.llvm.org/D63992>,
but as this diff shows, not every target will prefer that pattern.

Out of 4 targets for which i added tests all seem to be ok with inc-of-add for scalars,
but only X86 prefer that same pattern for vectors.

Here i'm adding a new TLI hook, always defaulting to the inc-of-add,
but adding AArch64,ARM,PowerPC overrides to prefer inc-of-add only for scalars.


Repository:
  rL LLVM

https://reviews.llvm.org/D64090

Files:
  include/llvm/CodeGen/TargetLowering.h
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64ISelLowering.h
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCISelLowering.h
  test/CodeGen/AArch64/inc-of-add.ll
  test/CodeGen/AArch64/sub-of-not.ll
  test/CodeGen/ARM/inc-of-add.ll
  test/CodeGen/ARM/sub-of-not.ll
  test/CodeGen/PowerPC/inc-of-add.ll
  test/CodeGen/PowerPC/sub-of-not.ll
  test/CodeGen/X86/sub-of-not.ll

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