[llvm] r364897 - [NFC][InstCombine] Revisit tests for "redundant shift input masking" (PR42456)

[Roman Lebedev via llvm-commits]

Author: lebedevri
Date: Tue Jul  2 03:02:25 2019
New Revision: 364897

URL: http://llvm.org/viewvc/llvm-project?rev=364897&view=rev
Log:
[NFC][InstCombine] Revisit tests for "redundant shift input masking" (PR42456)

Modified:
    llvm/trunk/test/Transforms/InstCombine/redundant-shift-input-masking.ll

Modified: llvm/trunk/test/Transforms/InstCombine/redundant-shift-input-masking.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/redundant-shift-input-masking.ll?rev=364897&r1=364896&r2=364897&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/redundant-shift-input-masking.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/redundant-shift-input-masking.ll Tue Jul  2 03:02:25 2019
@@ -8,29 +8,30 @@
 ; The mask is redundant, and can be dropped:
 ;   data outer>> nbits
 ; This is valid for both lshr and ashr in both positions and any combination.
+; We must *not* preserve 'exact' on that final right-shift.
 
 define i32 @t0_lshr(i32 %data, i32 %nbits) {
 ; CHECK-LABEL: @t0_lshr(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
-; CHECK-NEXT:    [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
+; CHECK-NEXT:    [[T2:%.*]] = lshr exact i32 [[T1]], [[NBITS]]
 ; CHECK-NEXT:    ret i32 [[T2]]
 ;
   %t0 = shl i32 -1, %nbits
   %t1 = and i32 %t0, %data
-  %t2 = lshr i32 %t1, %nbits
+  %t2 = lshr exact i32 %t1, %nbits ; while there, test that we *don't* propagate 'exact'
   ret i32 %t2
 }
 define i32 @t1_sshr(i32 %data, i32 %nbits) {
 ; CHECK-LABEL: @t1_sshr(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
-; CHECK-NEXT:    [[T2:%.*]] = ashr i32 [[T1]], [[NBITS]]
+; CHECK-NEXT:    [[T2:%.*]] = ashr exact i32 [[T1]], [[NBITS]]
 ; CHECK-NEXT:    ret i32 [[T2]]
 ;
   %t0 = shl i32 -1, %nbits
   %t1 = and i32 %t0, %data
-  %t2 = ashr i32 %t1, %nbits
+  %t2 = ashr exact i32 %t1, %nbits ; while there, test that we *don't* propagate 'exact'
   ret i32 %t2
 }
 
@@ -183,10 +184,29 @@ define i32 @t10_noncanonical_ashr_ashr_e
   ret i32 %t2
 }
 
+; Commutativity
+
+declare i32 @gen32()
+
+define i32 @t11_commutative(i32 %nbits) {
+; CHECK-LABEL: @t11_commutative(
+; CHECK-NEXT:    [[DATA:%.*]] = call i32 @gen32()
+; CHECK-NEXT:    [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT:    [[T1:%.*]] = and i32 [[DATA]], [[T0]]
+; CHECK-NEXT:    [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
+; CHECK-NEXT:    ret i32 [[T2]]
+;
+  %data = call i32 @gen32()
+  %t0 = shl i32 -1, %nbits
+  %t1 = and i32 %data, %t0 ; swapped
+  %t2 = lshr i32 %t1, %nbits
+  ret i32 %t2
+}
+
 ; Negative tests
 
-define i32 @n11(i32 %data, i32 %nbits) {
-; CHECK-LABEL: @n11(
+define i32 @n12(i32 %data, i32 %nbits) {
+; CHECK-LABEL: @n12(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 2147483647, [[NBITS:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
@@ -198,8 +218,8 @@ define i32 @n11(i32 %data, i32 %nbits) {
   ret i32 %t2
 }
 
-define i32 @n12(i32 %data, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n12(
+define i32 @n13(i32 %data, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n13(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 -1, [[NBITS0:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = lshr i32 [[T1]], [[NBITS1:%.*]]
@@ -211,8 +231,8 @@ define i32 @n12(i32 %data, i32 %nbits0,
   ret i32 %t2
 }
 
-define i32 @n13(i32 %data, i32 %nbits0, i32 %nbits1, i32 %nbits2) {
-; CHECK-LABEL: @n13(
+define i32 @n14(i32 %data, i32 %nbits0, i32 %nbits1, i32 %nbits2) {
+; CHECK-LABEL: @n14(
 ; CHECK-NEXT:    [[T0:%.*]] = lshr i32 [[DATA:%.*]], [[NBITS0:%.*]]
 ; CHECK-NEXT:    call void @use32(i32 [[T0]])
 ; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[T0]], [[NBITS1:%.*]]