[llvm] r364822 - GlobalISel: Verify G_MERGE_VALUES operand sizes

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 1 11:01:35 PDT 2019


Author: arsenm
Date: Mon Jul  1 11:01:35 2019
New Revision: 364822

URL: http://llvm.org/viewvc/llvm-project?rev=364822&view=rev
Log:
GlobalISel: Verify G_MERGE_VALUES operand sizes

Added:
    llvm/trunk/test/MachineVerifier/test_g_merge_values.mir
Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=364822&r1=364821&r2=364822&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Mon Jul  1 11:01:35 2019
@@ -1176,6 +1176,16 @@ void MachineVerifier::verifyPreISelGener
     LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
     if (DstTy.isVector() || SrcTy.isVector())
       report("G_MERGE_VALUES cannot operate on vectors", MI);
+
+    const unsigned NumOps = MI->getNumOperands();
+    if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
+      report("G_MERGE_VALUES result size is inconsistent", MI);
+
+    for (unsigned I = 2; I != NumOps; ++I) {
+      if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
+        report("G_MERGE_VALUES source types do not match", MI);
+    }
+
     break;
   }
   case TargetOpcode::G_UNMERGE_VALUES: {

Added: llvm/trunk/test/MachineVerifier/test_g_merge_values.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MachineVerifier/test_g_merge_values.mir?rev=364822&view=auto
==============================================================================
--- llvm/trunk/test/MachineVerifier/test_g_merge_values.mir (added)
+++ llvm/trunk/test/MachineVerifier/test_g_merge_values.mir Mon Jul  1 11:01:35 2019
@@ -0,0 +1,28 @@
+# RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+---
+name:            g_merge_values
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+    %0:_(s32) = IMPLICIT_DEF
+    %1:_(s32) = IMPLICIT_DEF
+    %2:_(<2 x s32>) = IMPLICIT_DEF
+    %3:_(<2 x s32>) = IMPLICIT_DEF
+
+    ; CHECK: Bad machine code: G_MERGE_VALUES cannot operate on vectors
+    %4:_(<4 x s32>) = G_MERGE_VALUES %2, %3
+
+    ; CHECK: Bad machine code: G_MERGE_VALUES result size is inconsistent
+    %5:_(s64) = G_MERGE_VALUES %0
+
+    ; CHECK: Bad machine code: G_MERGE_VALUES result size is inconsistent
+    %6:_(s64) = G_MERGE_VALUES %0, %1, %1
+
+    %7:_(s16) = IMPLICIT_DEF
+
+    ; CHECK: Bad machine code: G_MERGE_VALUES source types do not match
+    %8:_(s64) = G_MERGE_VALUES %0, %7
+
+...




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