[PATCH] D63411: [RISCV] Specify registers used in DWARF exception handling

[Alex Bradbury via Phabricator via llvm-commits]

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It looks like docs/ExceptionHandling.rst documents that for most targets, the same as the calling convention GPRs.

Ed, can you please update with a test? You should be able to copy test/Transforms/CallSiteSplitting/lpad.ll to something like test/CodeGen/RISCV/exception-pointer-register.ll then add riscv32 and riscv64 RUN lines and a comment that this test asserted prior to getExceptionPointerRegister and getExceptionSelectorRegister being implemented.


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