[llvm] r364765 - AMDGPU/GlobalISel: Improve icmp selection coverage.
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 1 06:34:27 PDT 2019
Author: arsenm
Date: Mon Jul 1 06:34:26 2019
New Revision: 364765
URL: http://llvm.org/viewvc/llvm-project?rev=364765&view=rev
Log:
AMDGPU/GlobalISel: Improve icmp selection coverage.
Select s64 eq/ne scalar icmp.
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp?rev=364765&r1=364764&r2=364765&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp Mon Jul 1 06:34:26 2019
@@ -317,8 +317,9 @@ bool AMDGPUInstructionSelector::selectG_
return false;
}
-static unsigned getV_CMPOpcode(CmpInst::Predicate P, unsigned Size) {
- assert(Size == 32 || Size == 64);
+static int getV_CMPOpcode(CmpInst::Predicate P, unsigned Size) {
+ if (Size != 32 && Size != 64)
+ return -1;
switch (P) {
default:
llvm_unreachable("Unknown condition code!");
@@ -345,12 +346,26 @@ static unsigned getV_CMPOpcode(CmpInst::
}
}
-static unsigned getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) {
- // FIXME: VI supports 64-bit comparse.
- assert(Size == 32);
+int AMDGPUInstructionSelector::getS_CMPOpcode(CmpInst::Predicate P,
+ unsigned Size) const {
+ if (Size == 64) {
+ if (!STI.hasScalarCompareEq64())
+ return -1;
+
+ switch (P) {
+ case CmpInst::ICMP_NE:
+ return AMDGPU::S_CMP_LG_U64;
+ case CmpInst::ICMP_EQ:
+ return AMDGPU::S_CMP_EQ_U64;
+ default:
+ return -1;
+ }
+ }
+
+ if (Size != 32)
+ return -1;
+
switch (P) {
- default:
- llvm_unreachable("Unknown condition code!");
case CmpInst::ICMP_NE:
return AMDGPU::S_CMP_LG_U32;
case CmpInst::ICMP_EQ:
@@ -371,6 +386,8 @@ static unsigned getS_CMPOpcode(CmpInst::
return AMDGPU::S_CMP_LT_U32;
case CmpInst::ICMP_ULE:
return AMDGPU::S_CMP_LE_U32;
+ default:
+ llvm_unreachable("Unknown condition code!");
}
}
@@ -382,12 +399,14 @@ bool AMDGPUInstructionSelector::selectG_
unsigned SrcReg = I.getOperand(2).getReg();
unsigned Size = RBI.getSizeInBits(SrcReg, MRI, TRI);
- // FIXME: VI supports 64-bit compares.
- assert(Size == 32);
+
+ auto Pred = (CmpInst::Predicate)I.getOperand(1).getPredicate();
unsigned CCReg = I.getOperand(0).getReg();
if (isSCC(CCReg, MRI)) {
- unsigned Opcode = getS_CMPOpcode((CmpInst::Predicate)I.getOperand(1).getPredicate(), Size);
+ int Opcode = getS_CMPOpcode(Pred, Size);
+ if (Opcode == -1)
+ return false;
MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode))
.add(I.getOperand(2))
.add(I.getOperand(3));
@@ -400,8 +419,10 @@ bool AMDGPUInstructionSelector::selectG_
return Ret;
}
- assert(Size == 32 || Size == 64);
- unsigned Opcode = getV_CMPOpcode((CmpInst::Predicate)I.getOperand(1).getPredicate(), Size);
+ int Opcode = getV_CMPOpcode(Pred, Size);
+ if (Opcode == -1)
+ return false;
+
MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode),
I.getOperand(0).getReg())
.add(I.getOperand(2))
@@ -984,7 +1005,9 @@ bool AMDGPUInstructionSelector::select(M
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
return selectG_INTRINSIC_W_SIDE_EFFECTS(I, CoverageInfo);
case TargetOpcode::G_ICMP:
- return selectG_ICMP(I);
+ if (selectG_ICMP(I))
+ return true;
+ return selectImpl(I, CoverageInfo);
case TargetOpcode::G_LOAD:
if (selectImpl(I, CoverageInfo))
return true;
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h?rev=364765&r1=364764&r2=364765&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h Mon Jul 1 06:34:26 2019
@@ -18,6 +18,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/IR/InstrTypes.h"
namespace {
#define GET_GLOBALISEL_PREDICATE_BITSET
@@ -74,6 +75,7 @@ private:
bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I,
CodeGenCoverage &CoverageInfo) const;
+ int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
bool selectG_ICMP(MachineInstr &I) const;
bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir?rev=364765&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir Mon Jul 1 06:34:26 2019
@@ -0,0 +1,595 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -pass-remarks-missed='gisel*' -global-isel-abort=2 -o - %s 2> %t | FileCheck -check-prefix=GFX8 %s
+# RUN: FileCheck -check-prefixes=ERR,GFX8-ERR %s < %t
+
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' -o - %s 2> %t | FileCheck -check-prefix=GFX6 %s
+# RUN: FileCheck -check-prefixes=ERR,GFX6-ERR %s < %t
+
+
+# ERR-NOT: remark
+
+# GFX6-ERR: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(eq), %0:sgpr(s64), %1:sgpr (in function: icmp_eq_s64_ss)
+# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(ne), %0:sgpr(s64), %1:sgpr (in function: icmp_ne_s64_ss)
+# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(slt), %0:sgpr(s64), %1:sgpr (in function: icmp_slt_s64_ss)
+# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(eq), %0:sgpr(p0), %1:sgpr (in function: icmp_eq_p0_ss)
+# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(eq), %0:sgpr(p1), %1:sgpr (in function: icmp_eq_p1_ss)
+# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(eq), %0:sgpr(p999), %1:sgpr (in function: icmp_eq_p999_ss)
+
+# GFX8-ERR: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(slt), %0:sgpr(s64), %1:sgpr (in function: icmp_slt_s64_ss)
+
+# ERR-NOT: remark
+
+---
+name: icmp_eq_s64_ss
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+ ; GFX8-LABEL: name: icmp_eq_s64_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
+ ; GFX8: S_CMP_EQ_U64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
+ ; GFX8: $scc = COPY [[COPY2]]
+ ; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
+ ; GFX8: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
+ ; GFX6-LABEL: name: icmp_eq_s64_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
+ ; GFX6: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
+ ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
+ ; GFX6: $scc = COPY [[COPY2]]
+ ; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
+ ; GFX6: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:sgpr(s64) = COPY $sgpr2_sgpr3
+ %2:scc(s1) = G_ICMP intpred(eq), %0, %1
+ %3:sgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_ne_s64_ss
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+ ; GFX8-LABEL: name: icmp_ne_s64_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
+ ; GFX8: S_CMP_LG_U64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
+ ; GFX8: $scc = COPY [[COPY2]]
+ ; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
+ ; GFX8: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
+ ; GFX6-LABEL: name: icmp_ne_s64_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
+ ; GFX6: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]
+ ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
+ ; GFX6: $scc = COPY [[COPY2]]
+ ; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
+ ; GFX6: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:sgpr(s64) = COPY $sgpr2_sgpr3
+ %2:scc(s1) = G_ICMP intpred(ne), %0, %1
+ %3:sgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_slt_s64_ss
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+ ; GFX8-LABEL: name: icmp_slt_s64_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
+ ; GFX8: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
+ ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
+ ; GFX8: $scc = COPY [[COPY2]]
+ ; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
+ ; GFX8: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
+ ; GFX6-LABEL: name: icmp_slt_s64_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
+ ; GFX6: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
+ ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
+ ; GFX6: $scc = COPY [[COPY2]]
+ ; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
+ ; GFX6: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:sgpr(s64) = COPY $sgpr2_sgpr3
+ %2:scc(s1) = G_ICMP intpred(slt), %0, %1
+ %3:sgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_eq_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GFX8-LABEL: name: icmp_eq_s64_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX8: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ ; GFX6-LABEL: name: icmp_eq_s64_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
+ %3:vgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_ne_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GFX8-LABEL: name: icmp_ne_s64_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX8: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_NE_U64_e64_]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ ; GFX6-LABEL: name: icmp_ne_s64_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_NE_U64_e64_]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_ICMP intpred(ne), %0, %1
+ %3:vgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_sgt_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GFX8-LABEL: name: icmp_sgt_s64_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX8: [[V_CMP_GT_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GT_I64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GT_I64_e64_]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ ; GFX6-LABEL: name: icmp_sgt_s64_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_CMP_GT_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GT_I64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GT_I64_e64_]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_ICMP intpred(sgt), %0, %1
+ %3:vgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_sge_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GFX8-LABEL: name: icmp_sge_s64_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX8: [[V_CMP_GE_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GE_I64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GE_I64_e64_]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ ; GFX6-LABEL: name: icmp_sge_s64_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_CMP_GE_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GE_I64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GE_I64_e64_]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_ICMP intpred(sge), %0, %1
+ %3:vgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_slt_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GFX8-LABEL: name: icmp_slt_s64_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX8: [[V_CMP_LT_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_I64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LT_I64_e64_]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ ; GFX6-LABEL: name: icmp_slt_s64_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_CMP_LT_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_I64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LT_I64_e64_]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_ICMP intpred(slt), %0, %1
+ %3:vgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_sle_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GFX8-LABEL: name: icmp_sle_s64_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX8: [[V_CMP_LE_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LE_I64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LE_I64_e64_]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ ; GFX6-LABEL: name: icmp_sle_s64_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_CMP_LE_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LE_I64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LE_I64_e64_]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_ICMP intpred(sle), %0, %1
+ %3:vgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_ugt_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GFX8-LABEL: name: icmp_ugt_s64_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX8: [[V_CMP_GT_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GT_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GT_U64_e64_]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ ; GFX6-LABEL: name: icmp_ugt_s64_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_CMP_GT_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GT_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GT_U64_e64_]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_ICMP intpred(ugt), %0, %1
+ %3:vgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_uge_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GFX8-LABEL: name: icmp_uge_s64_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX8: [[V_CMP_GE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GE_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GE_U64_e64_]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ ; GFX6-LABEL: name: icmp_uge_s64_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_CMP_GE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GE_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GE_U64_e64_]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_ICMP intpred(uge), %0, %1
+ %3:vgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_ult_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GFX8-LABEL: name: icmp_ult_s64_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX8: [[V_CMP_LT_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LT_U64_e64_]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ ; GFX6-LABEL: name: icmp_ult_s64_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_CMP_LT_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LT_U64_e64_]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_ICMP intpred(ult), %0, %1
+ %3:vgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_ule_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GFX8-LABEL: name: icmp_ule_s64_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX8: [[V_CMP_LE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LE_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LE_U64_e64_]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ ; GFX6-LABEL: name: icmp_ule_s64_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_CMP_LE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LE_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LE_U64_e64_]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_ICMP intpred(ule), %0, %1
+ %3:vgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_eq_p0_ss
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+ ; GFX8-LABEL: name: icmp_eq_p0_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
+ ; GFX8: S_CMP_EQ_U64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
+ ; GFX8: $scc = COPY [[COPY2]]
+ ; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
+ ; GFX8: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
+ ; GFX6-LABEL: name: icmp_eq_p0_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(p0) = COPY $sgpr2_sgpr3
+ ; GFX6: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
+ ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
+ ; GFX6: $scc = COPY [[COPY2]]
+ ; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
+ ; GFX6: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %1:sgpr(p0) = COPY $sgpr2_sgpr3
+ %2:scc(s1) = G_ICMP intpred(eq), %0, %1
+ %3:sgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_eq_p1_ss
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+ ; GFX8-LABEL: name: icmp_eq_p1_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
+ ; GFX8: S_CMP_EQ_U64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
+ ; GFX8: $scc = COPY [[COPY2]]
+ ; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
+ ; GFX8: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
+ ; GFX6-LABEL: name: icmp_eq_p1_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3
+ ; GFX6: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](p1), [[COPY1]]
+ ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
+ ; GFX6: $scc = COPY [[COPY2]]
+ ; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
+ ; GFX6: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
+ %0:sgpr(p1) = COPY $sgpr0_sgpr1
+ %1:sgpr(p1) = COPY $sgpr2_sgpr3
+ %2:scc(s1) = G_ICMP intpred(eq), %0, %1
+ %3:sgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_eq_p999_ss
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+ ; GFX8-LABEL: name: icmp_eq_p999_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
+ ; GFX8: S_CMP_EQ_U64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
+ ; GFX8: $scc = COPY [[COPY2]]
+ ; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
+ ; GFX8: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
+ ; GFX6-LABEL: name: icmp_eq_p999_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(p999) = COPY $sgpr0_sgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(p999) = COPY $sgpr2_sgpr3
+ ; GFX6: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](p999), [[COPY1]]
+ ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
+ ; GFX6: $scc = COPY [[COPY2]]
+ ; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
+ ; GFX6: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
+ %0:sgpr(p999) = COPY $sgpr0_sgpr1
+ %1:sgpr(p999) = COPY $sgpr2_sgpr3
+ %2:scc(s1) = G_ICMP intpred(eq), %0, %1
+ %3:sgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_eq_p0_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GFX8-LABEL: name: icmp_eq_p0_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX8: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ ; GFX6-LABEL: name: icmp_eq_p0_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(p0) = COPY $vgpr0_vgpr1
+ %1:vgpr(p0) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
+ %3:vgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_eq_p1_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GFX8-LABEL: name: icmp_eq_p1_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX8: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ ; GFX6-LABEL: name: icmp_eq_p1_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(p1) = COPY $vgpr0_vgpr1
+ %1:vgpr(p1) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
+ %3:vgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: icmp_eq_p999_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GFX8-LABEL: name: icmp_eq_p999_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX8: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ ; GFX6-LABEL: name: icmp_eq_p999_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(p999) = COPY $vgpr0_vgpr1
+ %1:vgpr(p999) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
+ %3:vgpr(s32) = G_ZEXT %2
+ S_ENDPGM 0, implicit %3
+
+...
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