[PATCH] D64002: AMDGPU/GlobalISel: Tolerate copies with no type set

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: tstellar, nhaehnle.
Herald added subscribers: Petar.Avramovic, t-tye, tpr, dstuttard, kristof.beyls, rovka, yaxunl, wdng, jvesely, kzhuravl.

isVCC has the same bug, but isn't used in a context where it can cause
a problem.


https://reviews.llvm.org/D64002

Files:
  lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir


Index: test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
===================================================================
--- test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
+++ test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
@@ -75,4 +75,60 @@
     %7:vgpr(s32) = G_SELECT %6, %1, %5
     G_STORE %7, %0 :: (store 4, addrspace 1)
 ...
+
+---
+
+name:            copy_sgpr_no_type
+legalized:       true
+regBankSelected: true
+
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; GCN-LABEL: name: copy_sgpr_no_type
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: S_ENDPGM 0, implicit [[COPY]]
+    %0:sreg_32_xm0 = COPY $sgpr0
+    %1:sreg_32_xm0 = COPY %0
+    S_ENDPGM 0, implicit %1
+
+...
+
+---
+
+name:            copy_vgpr_no_type
+legalized:       true
+regBankSelected: true
+
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; GCN-LABEL: name: copy_vgpr_no_type
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: S_ENDPGM 0, implicit [[COPY]]
+    %0:vgpr_32 = COPY $vgpr0
+    %1:vgpr_32 = COPY %0
+    S_ENDPGM 0, implicit %1
+
+...
+
 ---
+
+name:            copy_maybe_vcc
+legalized:       true
+regBankSelected: true
+
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; GCN-LABEL: name: copy_maybe_vcc
+    ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; GCN: S_ENDPGM 0, implicit [[COPY]]
+    %0:sreg_64_xexec = COPY $sgpr0_sgpr1
+    %1:sreg_64_xexec  = COPY %0
+    S_ENDPGM 0, implicit %1
+
+...
Index: lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -66,9 +66,12 @@
   auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
   const TargetRegisterClass *RC =
       RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
-  if (RC)
-    return RC->getID() == AMDGPU::SReg_32_XM0RegClassID &&
-           MRI.getType(Reg).getSizeInBits() == 1;
+  if (RC) {
+    if (RC->getID() != AMDGPU::SReg_32_XM0RegClassID)
+      return false;
+    const LLT Ty = MRI.getType(Reg);
+    return Ty.isValid() && Ty.getSizeInBits() == 1;
+  }
 
   const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
   return RB->getID() == AMDGPU::SCCRegBankID;


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