[PATCH] D54409: PowerPC/SPE: Fix load/store handling for SPE

Mon Jul 1 01:17:21 PDT 2019

kthomsen added a comment.

I found one more patch, where I'm not sure if we already had this one and removed it, or if I simply forgot to post it.

  --- PPCISelLowering.orig.cpp    2019-07-01 09:08:11.444438400 +0200
  +++ PPCISelLowering.cpp 2019-07-01 08:45:16.911244700 +0200
  @@ -3011,7 +3114,7 @@ SDValue PPCTargetLowering::LowerVAARG(SD
                                       VAListPtr, MachinePointerInfo(SV), MVT::i8);
     InChain = GprIndex.getValue(1);

  -  if (VT == MVT::i64) {
  +  if ((VT == MVT::i64) || (hasSPE() && (VT == MVT::f64))) {
       // Check if GprIndex is even
       SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
                                    DAG.getConstant(1, dl, MVT::i32));

This has been done, to make sure the register pair for a f64 is the same (even register) like when using i64.

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54409/new/

https://reviews.llvm.org/D54409