[llvm] r364434 - [X86][SSE] X86TargetLowering::isCommutativeBinOp - add PMULDQ

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Wed Jun 26 07:58:11 2019
New Revision: 364434

URL: http://llvm.org/viewvc/llvm-project?rev=364434&view=rev
Log:
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PMULDQ

Allows narrowInsertExtractVectorBinOp to reduce vector size instead of the more restricted SimplifyDemandedVectorEltsForTargetNode

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=364434&r1=364433&r2=364434&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jun 26 07:58:11 2019
@@ -28587,6 +28587,7 @@ bool X86TargetLowering::isCommutativeBin
   switch (Opcode) {
   // TODO: Add more X86ISD opcodes once we have test coverage.
   case X86ISD::PCMPEQ:
+  case X86ISD::PMULDQ:
   case X86ISD::PMULUDQ:
   case X86ISD::FMAXC:
   case X86ISD::FMINC:
@@ -34007,9 +34008,6 @@ bool X86TargetLowering::SimplifyDemanded
           insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits);
       return TLO.CombineTo(Op, Insert);
     }
-      // Arithmetic Ops.
-    case X86ISD::PMULDQ:
-    case X86ISD::PMULUDQ:
       // Target Shuffles.
     case X86ISD::PSHUFB:
     case X86ISD::UNPCKL: