[PATCH] D63815: [DAGCombine] visitEXTRACT_SUBVECTOR - 'little to big' extract_subvector(bitcast()) support

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: efriedma, spatel, MatzeB, aemerson, evandro.
Herald added subscribers: kristof.beyls, javed.absar.
Herald added a project: LLVM.

This moves the X86 specific transform from rL364407 <https://reviews.llvm.org/rL364407> into DAGCombiner to generically handle 'little to big' cases (e.g. extract_subvector(v2i64 bitcast(v16i8))), this allows us to remove both the x86 implementation and the aarch64 bitcast(extract_subvector(bitcast())) combine (note none of the regressions are due to removing this).

We see a number of regressions which is why I went for making it x86 in the first place:

AArch64's poor handling of shuffle(bitcast(),bitcast()) cases - AArch64ISD::DUPLANE cases in particular as well as "extract high" patterns.

The merge-store.ll change is interesting - AArch64TargetLowering::allowsMisalignedMemoryAccesses permits 'fast' unaligned v2i64 stores in all cases which is being exposed by removing the bitcast.

Most likely we need to address these issues before this patch can proceed - I'm happy to help if someone can suggest what is the most critical to fix first.


Repository:
  rL LLVM

https://reviews.llvm.org/D63815

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/AArch64/arm64-neon-2velem.ll
  test/CodeGen/AArch64/arm64-vcvt_f.ll
  test/CodeGen/AArch64/merge-store.ll
  test/CodeGen/AArch64/vector-fcopysign.ll
  test/CodeGen/ARM/combine-vmovdrr.ll

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