[llvm] r363802 - [TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_INREG -> ANY/ZERO_EXTEND_VECTOR_INREG
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 24 23:41:31 PDT 2019
I've committed an even more reduced version of Eric's test in r364272.
I attempted to fix the issue by adding setOperationAction lines for
ISD::ANY_EXTEND_VECTOR_INREG to all the places that had
SIGN/ZERO_EXTEND_VECTOR_INREG already. And the modified LowerOperation to
call LowerEXTEND_VECTOR_INREG. And then fixed the hasInt256() path inside
of that to pick between ZERO_EXTEND/SIGN_EXTEND/ANY_EXTEND.
Unforunately, setting MVT::v8i16, MVT::v4i32, MVT::v2i64
ISD::ANY_EXTEND_VECTOR_INREG to Legal is leading to a bunch of test
failures. Leaving it out passes all tests and still fixes Eric's test case.
But I feel like it might lead to a DAG combine infinite loop since
ANY_EXTEND_VECTOR_INREG will become shuffle vector which will become
ZERO_VECTOR_INREG and then SimplifyDemandedBits might try to turn that back
into ANY_EXTEND_VECTOR_INREG repeating the cycle.
~Craig
On Mon, Jun 24, 2019 at 6:52 PM Eric Christopher <echristo at gmail.com> wrote:
> Thanks Craig!
>
> -eric
>
> On Mon, Jun 24, 2019 at 6:34 PM Craig Topper <craig.topper at gmail.com>
> wrote:
> >
> > Reverted this and obviously related patches in r364264. I'll see about
> committing Eric's test and maybe trying fix this issue later tonight
> >
> > ~Craig
> >
> >
> > On Mon, Jun 24, 2019 at 6:19 PM Eric Christopher <echristo at gmail.com>
> wrote:
> >>
> >> Here's a pretty small testcase.
> >>
> >> Craig has said he's working on the revert.
> >>
> >> -eric
> >>
> >> On Mon, Jun 24, 2019 at 4:58 PM Eric Christopher <echristo at gmail.com>
> wrote:
> >> >
> >> > Hi Simon,
> >> >
> >> > I'm seeing at least one occurrence of "fatal error: error in backend:
> >> > Cannot emit physreg copy instruction" after this patch attempting to
> >> > build an mp4 library. I'm not entirely sure from where or how (inline
> >> > assembly, normal code, etc), but wanted to let you know as we
> >> > investigate. The code has, of course, been building up to this point
> >> > so my inclination is to revert and get a testcase reduced out of the
> >> > sources.
> >> >
> >> > Thoughts?
> >> >
> >> > -eric
> >> >
> >> > On Wed, Jun 19, 2019 at 6:54 AM Simon Pilgrim via llvm-commits
> >> > <llvm-commits at lists.llvm.org> wrote:
> >> > >
> >> > > Author: rksimon
> >> > > Date: Wed Jun 19 06:58:02 2019
> >> > > New Revision: 363802
> >> > >
> >> > > URL: http://llvm.org/viewvc/llvm-project?rev=363802&view=rev
> >> > > Log:
> >> > > [TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_INREG ->
> ANY/ZERO_EXTEND_VECTOR_INREG
> >> > >
> >> > > Simplify SIGN_EXTEND_VECTOR_INREG if the extended bits are not
> required/known zero.
> >> > >
> >> > > Matches what we already do for SIGN_EXTEND.
> >> > >
> >> > > Modified:
> >> > > llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> >> > > llvm/trunk/test/CodeGen/X86/pmul.ll
> >> > > llvm/trunk/test/CodeGen/X86/xop-ifma.ll
> >> > >
> >> > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> >> > > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=363802&r1=363801&r2=363802&view=diff
> >> > >
> ==============================================================================
> >> > > --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> (original)
> >> > > +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun
> 19 06:58:02 2019
> >> > > @@ -1413,9 +1413,11 @@ bool TargetLowering::SimplifyDemandedBit
> >> > > bool IsVecInReg = Op.getOpcode() ==
> ISD::SIGN_EXTEND_VECTOR_INREG;
> >> > >
> >> > > // If none of the top bits are demanded, convert this into an
> any_extend.
> >> > > - // TODO: Add SIGN_EXTEND_VECTOR_INREG -
> ANY_EXTEND_VECTOR_INREG fold.
> >> > > - if (DemandedBits.getActiveBits() <= InBits && !IsVecInReg)
> >> > > - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
> dl, VT, Src));
> >> > > + if (DemandedBits.getActiveBits() <= InBits)
> >> > > + return TLO.CombineTo(
> >> > > + Op, TLO.DAG.getNode(IsVecInReg ?
> ISD::ANY_EXTEND_VECTOR_INREG
> >> > > + : ISD::ANY_EXTEND,
> >> > > + dl, VT, Src));
> >> > >
> >> > > APInt InDemandedBits = DemandedBits.trunc(InBits);
> >> > > APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
> >> > > @@ -1434,9 +1436,11 @@ bool TargetLowering::SimplifyDemandedBit
> >> > > Known = Known.sext(BitWidth);
> >> > >
> >> > > // If the sign bit is known zero, convert this to a zero
> extend.
> >> > > - // TODO: Add SIGN_EXTEND_VECTOR_INREG -
> ZERO_EXTEND_VECTOR_INREG fold.
> >> > > - if (Known.isNonNegative() && !IsVecInReg)
> >> > > - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
> dl, VT, Src));
> >> > > + if (Known.isNonNegative())
> >> > > + return TLO.CombineTo(
> >> > > + Op, TLO.DAG.getNode(IsVecInReg ?
> ISD::ZERO_EXTEND_VECTOR_INREG
> >> > > + : ISD::ZERO_EXTEND,
> >> > > + dl, VT, Src));
> >> > > break;
> >> > > }
> >> > > case ISD::ANY_EXTEND: {
> >> > >
> >> > > Modified: llvm/trunk/test/CodeGen/X86/pmul.ll
> >> > > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pmul.ll?rev=363802&r1=363801&r2=363802&view=diff
> >> > >
> ==============================================================================
> >> > > --- llvm/trunk/test/CodeGen/X86/pmul.ll (original)
> >> > > +++ llvm/trunk/test/CodeGen/X86/pmul.ll Wed Jun 19 06:58:02 2019
> >> > > @@ -1326,15 +1326,13 @@ define <8 x i64> @mul_v8i64_sext(<8 x i1
> >> > > ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,2,3]
> >> > > ; SSE41-NEXT: pmovsxwq %xmm3, %xmm6
> >> > > ; SSE41-NEXT: pmovsxwq %xmm0, %xmm7
> >> > > -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,0,1]
> >> > > -; SSE41-NEXT: pmovsxdq %xmm0, %xmm3
> >> > > +; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,2,3,3]
> >> > > ; SSE41-NEXT: pmuldq %xmm4, %xmm3
> >> > > -; SSE41-NEXT: pmovsxdq %xmm2, %xmm2
> >> > > +; SSE41-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero
> >> > > ; SSE41-NEXT: pmuldq %xmm5, %xmm2
> >> > > -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1]
> >> > > -; SSE41-NEXT: pmovsxdq %xmm0, %xmm4
> >> > > +; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,2,3,3]
> >> > > ; SSE41-NEXT: pmuldq %xmm6, %xmm4
> >> > > -; SSE41-NEXT: pmovsxdq %xmm1, %xmm0
> >> > > +; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero
> >> > > ; SSE41-NEXT: pmuldq %xmm7, %xmm0
> >> > > ; SSE41-NEXT: movdqa %xmm4, %xmm1
> >> > > ; SSE41-NEXT: retq
> >> > >
> >> > > Modified: llvm/trunk/test/CodeGen/X86/xop-ifma.ll
> >> > > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xop-ifma.ll?rev=363802&r1=363801&r2=363802&view=diff
> >> > >
> ==============================================================================
> >> > > --- llvm/trunk/test/CodeGen/X86/xop-ifma.ll (original)
> >> > > +++ llvm/trunk/test/CodeGen/X86/xop-ifma.ll Wed Jun 19 06:58:02 2019
> >> > > @@ -67,12 +67,10 @@ define <8 x i32> @test_mul_v8i32_add_v8i
> >> > > define <4 x i64> @test_mulx_v4i32_add_v4i64(<4 x i32> %a0, <4 x
> i32> %a1, <4 x i64> %a2) {
> >> > > ; XOP-AVX1-LABEL: test_mulx_v4i32_add_v4i64:
> >> > > ; XOP-AVX1: # %bb.0:
> >> > > -; XOP-AVX1-NEXT: vpmovsxdq %xmm0, %xmm3
> >> > > -; XOP-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
> >> > > -; XOP-AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
> >> > > -; XOP-AVX1-NEXT: vpmovsxdq %xmm1, %xmm4
> >> > > -; XOP-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
> >> > > -; XOP-AVX1-NEXT: vpmovsxdq %xmm1, %xmm1
> >> > > +; XOP-AVX1-NEXT: vpmovzxdq {{.*#+}} xmm3 =
> xmm0[0],zero,xmm0[1],zero
> >> > > +; XOP-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,3,3]
> >> > > +; XOP-AVX1-NEXT: vpmovzxdq {{.*#+}} xmm4 =
> xmm1[0],zero,xmm1[1],zero
> >> > > +; XOP-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
> >> > > ; XOP-AVX1-NEXT: vextractf128 $1, %ymm2, %xmm5
> >> > > ; XOP-AVX1-NEXT: vpmacsdql %xmm5, %xmm1, %xmm0, %xmm0
> >> > > ; XOP-AVX1-NEXT: vpmacsdql %xmm2, %xmm4, %xmm3, %xmm1
> >> > >
> >> > >
> >> > > _______________________________________________
> >> > > llvm-commits mailing list
> >> > > llvm-commits at lists.llvm.org
> >> > > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>
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