[llvm] r364072 - [X86] isBinOp - move commutative ops to isCommutativeBinOp. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Jun 21 09:23:28 2019
New Revision: 364072

URL: http://llvm.org/viewvc/llvm-project?rev=364072&view=rev
Log:
[X86] isBinOp - move commutative ops to isCommutativeBinOp. NFCI.

TargetLoweringBase::isBinOp checks isCommutativeBinOp as a fallback, so don't duplicate.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=364072&r1=364071&r2=364072&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 21 09:23:28 2019
@@ -28545,17 +28545,12 @@ bool X86TargetLowering::isVectorShiftByS
 
 bool X86TargetLowering::isBinOp(unsigned Opcode) const {
   switch (Opcode) {
+  // These are non-commutative binops.
   // TODO: Add more X86ISD opcodes once we have test coverage.
   case X86ISD::ANDNP:
-  case X86ISD::PMULUDQ:
   case X86ISD::FMAX:
   case X86ISD::FMIN:
-  case X86ISD::FMAXC:
-  case X86ISD::FMINC:
-  case X86ISD::FAND:
   case X86ISD::FANDN:
-  case X86ISD::FOR:
-  case X86ISD::FXOR:
     return true;
   }
 
@@ -28566,6 +28561,11 @@ bool X86TargetLowering::isCommutativeBin
   switch (Opcode) {
   // TODO: Add more X86ISD opcodes once we have test coverage.
   case X86ISD::PMULUDQ:
+  case X86ISD::FMAXC:
+  case X86ISD::FMINC:
+  case X86ISD::FAND:
+  case X86ISD::FOR:
+  case X86ISD::FXOR:
     return true;
   }