[llvm] r364037 - [ARM] Add a batch of similarly encoded MVE instructions.
Simon Tatham via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 21 05:13:59 PDT 2019
Author: statham
Date: Fri Jun 21 05:13:59 2019
New Revision: 364037
URL: http://llvm.org/viewvc/llvm-project?rev=364037&view=rev
Log:
[ARM] Add a batch of similarly encoded MVE instructions.
Summary:
This adds the `MVE_qDest_qSrc` superclass and all instructions that
inherit from it. It's not the complete class of _everything_ with a
q-register as both destination and source; it's a subset of them that
all have similar encodings (but it would have been hopelessly unwieldy
to call it anything like MVE_111x11100).
This category includes add/sub with carry; long multiplies; halving
multiplies; multiply and accumulate, and some more complex
instructions.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62677
Added:
llvm/trunk/test/MC/ARM/mve-qdest-qsrc.s (with props)
llvm/trunk/test/MC/Disassembler/ARM/mve-qdest-qsrc.txt (with props)
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td?rev=364037&r1=364036&r2=364037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td Fri Jun 21 05:13:59 2019
@@ -2404,6 +2404,284 @@ def MVE_VCMPs32r : MVE_VCMPqrs<"s32", 0b
// end of MVE compares
+// start of MVE_qDest_qSrc
+
+class MVE_qDest_qSrc<string iname, string suffix, dag oops, dag iops,
+ string ops, vpred_ops vpred, string cstr,
+ list<dag> pattern=[]>
+ : MVE_p<oops, iops, NoItinerary, iname, suffix,
+ ops, vpred, cstr, pattern> {
+ bits<4> Qd;
+ bits<4> Qm;
+
+ let Inst{25-23} = 0b100;
+ let Inst{22} = Qd{3};
+ let Inst{15-13} = Qd{2-0};
+ let Inst{11-9} = 0b111;
+ let Inst{6} = 0b0;
+ let Inst{5} = Qm{3};
+ let Inst{4} = 0b0;
+ let Inst{3-1} = Qm{2-0};
+}
+
+class MVE_VQxDMLxDH<string iname, bit exch, bit round, bit subtract,
+ string suffix, bits<2> size, list<dag> pattern=[]>
+ : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+ (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+ vpred_r, "", pattern> {
+ bits<4> Qn;
+
+ let Inst{28} = subtract;
+ let Inst{21-20} = size;
+ let Inst{19-17} = Qn{2-0};
+ let Inst{16} = 0b0;
+ let Inst{12} = exch;
+ let Inst{8} = 0b0;
+ let Inst{7} = Qn{3};
+ let Inst{0} = round;
+}
+
+multiclass MVE_VQxDMLxDH_multi<string iname, bit exch,
+ bit round, bit subtract> {
+ def s8 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s8", 0b00>;
+ def s16 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s16", 0b01>;
+ def s32 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s32", 0b10>;
+}
+
+defm MVE_VQDMLADH : MVE_VQxDMLxDH_multi<"vqdmladh", 0b0, 0b0, 0b0>;
+defm MVE_VQDMLADHX : MVE_VQxDMLxDH_multi<"vqdmladhx", 0b1, 0b0, 0b0>;
+defm MVE_VQRDMLADH : MVE_VQxDMLxDH_multi<"vqrdmladh", 0b0, 0b1, 0b0>;
+defm MVE_VQRDMLADHX : MVE_VQxDMLxDH_multi<"vqrdmladhx", 0b1, 0b1, 0b0>;
+defm MVE_VQDMLSDH : MVE_VQxDMLxDH_multi<"vqdmlsdh", 0b0, 0b0, 0b1>;
+defm MVE_VQDMLSDHX : MVE_VQxDMLxDH_multi<"vqdmlsdhx", 0b1, 0b0, 0b1>;
+defm MVE_VQRDMLSDH : MVE_VQxDMLxDH_multi<"vqrdmlsdh", 0b0, 0b1, 0b1>;
+defm MVE_VQRDMLSDHX : MVE_VQxDMLxDH_multi<"vqrdmlsdhx", 0b1, 0b1, 0b1>;
+
+class MVE_VCMUL<string iname, string suffix, bit size, list<dag> pattern=[]>
+ : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+ (ins MQPR:$Qn, MQPR:$Qm, complexrotateop:$rot),
+ "$Qd, $Qn, $Qm, $rot", vpred_r, "", pattern> {
+ bits<4> Qn;
+ bits<2> rot;
+
+ let Inst{28} = size;
+ let Inst{21-20} = 0b11;
+ let Inst{19-17} = Qn{2-0};
+ let Inst{16} = 0b0;
+ let Inst{12} = rot{1};
+ let Inst{8} = 0b0;
+ let Inst{7} = Qn{3};
+ let Inst{0} = rot{0};
+
+ let Predicates = [HasMVEFloat];
+}
+
+def MVE_VCMULf16 : MVE_VCMUL<"vcmul", "f16", 0b0>;
+def MVE_VCMULf32 : MVE_VCMUL<"vcmul", "f32", 0b1>;
+
+class MVE_VMULL<string iname, string suffix, bit bit_28, bits<2> bits_21_20,
+ bit T, list<dag> pattern=[]>
+ : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+ (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+ vpred_r, "", pattern> {
+ bits<4> Qd;
+ bits<4> Qn;
+ bits<4> Qm;
+
+ let Inst{28} = bit_28;
+ let Inst{21-20} = bits_21_20;
+ let Inst{19-17} = Qn{2-0};
+ let Inst{16} = 0b1;
+ let Inst{12} = T;
+ let Inst{8} = 0b0;
+ let Inst{7} = Qn{3};
+ let Inst{0} = 0b0;
+}
+
+multiclass MVE_VMULL_multi<string iname, string suffix,
+ bit bit_28, bits<2> bits_21_20> {
+ def bh : MVE_VMULL<iname # "b", suffix, bit_28, bits_21_20, 0b0>;
+ def th : MVE_VMULL<iname # "t", suffix, bit_28, bits_21_20, 0b1>;
+}
+
+// For integer multiplies, bits 21:20 encode size, and bit 28 signedness.
+// For polynomial multiplies, bits 21:20 take the unused value 0b11, and
+// bit 28 switches to encoding the size.
+
+defm MVE_VMULLs8 : MVE_VMULL_multi<"vmull", "s8", 0b0, 0b00>;
+defm MVE_VMULLs16 : MVE_VMULL_multi<"vmull", "s16", 0b0, 0b01>;
+defm MVE_VMULLs32 : MVE_VMULL_multi<"vmull", "s32", 0b0, 0b10>;
+defm MVE_VMULLu8 : MVE_VMULL_multi<"vmull", "u8", 0b1, 0b00>;
+defm MVE_VMULLu16 : MVE_VMULL_multi<"vmull", "u16", 0b1, 0b01>;
+defm MVE_VMULLu32 : MVE_VMULL_multi<"vmull", "u32", 0b1, 0b10>;
+defm MVE_VMULLp8 : MVE_VMULL_multi<"vmull", "p8", 0b0, 0b11>;
+defm MVE_VMULLp16 : MVE_VMULL_multi<"vmull", "p16", 0b1, 0b11>;
+
+class MVE_VxMULH<string iname, string suffix, bit U, bits<2> size,
+ bit round, list<dag> pattern=[]>
+ : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+ (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+ vpred_r, "", pattern> {
+ bits<4> Qn;
+
+ let Inst{28} = U;
+ let Inst{21-20} = size;
+ let Inst{19-17} = Qn{2-0};
+ let Inst{16} = 0b1;
+ let Inst{12} = round;
+ let Inst{8} = 0b0;
+ let Inst{7} = Qn{3};
+ let Inst{0} = 0b1;
+}
+
+def MVE_VMULHs8 : MVE_VxMULH<"vmulh", "s8", 0b0, 0b00, 0b0>;
+def MVE_VMULHs16 : MVE_VxMULH<"vmulh", "s16", 0b0, 0b01, 0b0>;
+def MVE_VMULHs32 : MVE_VxMULH<"vmulh", "s32", 0b0, 0b10, 0b0>;
+def MVE_VMULHu8 : MVE_VxMULH<"vmulh", "u8", 0b1, 0b00, 0b0>;
+def MVE_VMULHu16 : MVE_VxMULH<"vmulh", "u16", 0b1, 0b01, 0b0>;
+def MVE_VMULHu32 : MVE_VxMULH<"vmulh", "u32", 0b1, 0b10, 0b0>;
+
+def MVE_VRMULHs8 : MVE_VxMULH<"vrmulh", "s8", 0b0, 0b00, 0b1>;
+def MVE_VRMULHs16 : MVE_VxMULH<"vrmulh", "s16", 0b0, 0b01, 0b1>;
+def MVE_VRMULHs32 : MVE_VxMULH<"vrmulh", "s32", 0b0, 0b10, 0b1>;
+def MVE_VRMULHu8 : MVE_VxMULH<"vrmulh", "u8", 0b1, 0b00, 0b1>;
+def MVE_VRMULHu16 : MVE_VxMULH<"vrmulh", "u16", 0b1, 0b01, 0b1>;
+def MVE_VRMULHu32 : MVE_VxMULH<"vrmulh", "u32", 0b1, 0b10, 0b1>;
+
+class MVE_VxMOVxN<string iname, string suffix, bit bit_28, bit bit_17,
+ bits<2> size, bit T, list<dag> pattern=[]>
+ : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+ (ins MQPR:$Qd_src, MQPR:$Qm), "$Qd, $Qm",
+ vpred_n, "$Qd = $Qd_src", pattern> {
+
+ let Inst{28} = bit_28;
+ let Inst{21-20} = 0b11;
+ let Inst{19-18} = size;
+ let Inst{17} = bit_17;
+ let Inst{16} = 0b1;
+ let Inst{12} = T;
+ let Inst{8} = 0b0;
+ let Inst{7} = !if(!eq(bit_17, 0), 1, 0);
+ let Inst{0} = 0b1;
+}
+
+multiclass MVE_VxMOVxN_halves<string iname, string suffix,
+ bit bit_28, bit bit_17, bits<2> size> {
+ def bh : MVE_VxMOVxN<iname # "b", suffix, bit_28, bit_17, size, 0b0>;
+ def th : MVE_VxMOVxN<iname # "t", suffix, bit_28, bit_17, size, 0b1>;
+}
+
+defm MVE_VMOVNi16 : MVE_VxMOVxN_halves<"vmovn", "i16", 0b1, 0b0, 0b00>;
+defm MVE_VMOVNi32 : MVE_VxMOVxN_halves<"vmovn", "i32", 0b1, 0b0, 0b01>;
+defm MVE_VQMOVNs16 : MVE_VxMOVxN_halves<"vqmovn", "s16", 0b0, 0b1, 0b00>;
+defm MVE_VQMOVNs32 : MVE_VxMOVxN_halves<"vqmovn", "s32", 0b0, 0b1, 0b01>;
+defm MVE_VQMOVNu16 : MVE_VxMOVxN_halves<"vqmovn", "u16", 0b1, 0b1, 0b00>;
+defm MVE_VQMOVNu32 : MVE_VxMOVxN_halves<"vqmovn", "u32", 0b1, 0b1, 0b01>;
+defm MVE_VQMOVUNs16 : MVE_VxMOVxN_halves<"vqmovun", "s16", 0b0, 0b0, 0b00>;
+defm MVE_VQMOVUNs32 : MVE_VxMOVxN_halves<"vqmovun", "s32", 0b0, 0b0, 0b01>;
+
+class MVE_VCVT_ff<string iname, string suffix, bit op, bit T,
+ list<dag> pattern=[]>
+ : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
+ "$Qd, $Qm", vpred_n, "$Qd = $Qd_src", pattern> {
+ let Inst{28} = op;
+ let Inst{21-16} = 0b111111;
+ let Inst{12} = T;
+ let Inst{8-7} = 0b00;
+ let Inst{0} = 0b1;
+
+ let Predicates = [HasMVEFloat];
+}
+
+multiclass MVE_VCVT_ff_halves<string suffix, bit op> {
+ def bh : MVE_VCVT_ff<"vcvtb", suffix, op, 0b0>;
+ def th : MVE_VCVT_ff<"vcvtt", suffix, op, 0b1>;
+}
+
+defm MVE_VCVTf16f32 : MVE_VCVT_ff_halves<"f16.f32", 0b0>;
+defm MVE_VCVTf32f16 : MVE_VCVT_ff_halves<"f32.f16", 0b1>;
+
+class MVE_VxCADD<string iname, string suffix, bits<2> size, bit halve,
+ list<dag> pattern=[]>
+ : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+ (ins MQPR:$Qn, MQPR:$Qm, complexrotateopodd:$rot),
+ "$Qd, $Qn, $Qm, $rot", vpred_r, "",
+ pattern> {
+ bits<4> Qn;
+ bit rot;
+
+ let Inst{28} = halve;
+ let Inst{21-20} = size;
+ let Inst{19-17} = Qn{2-0};
+ let Inst{16} = 0b0;
+ let Inst{12} = rot;
+ let Inst{8} = 0b1;
+ let Inst{7} = Qn{3};
+ let Inst{0} = 0b0;
+}
+
+def MVE_VCADDi8 : MVE_VxCADD<"vcadd", "i8", 0b00, 0b1>;
+def MVE_VCADDi16 : MVE_VxCADD<"vcadd", "i16", 0b01, 0b1>;
+def MVE_VCADDi32 : MVE_VxCADD<"vcadd", "i32", 0b10, 0b1>;
+
+def MVE_VHCADDs8 : MVE_VxCADD<"vhcadd", "s8", 0b00, 0b0>;
+def MVE_VHCADDs16 : MVE_VxCADD<"vhcadd", "s16", 0b01, 0b0>;
+def MVE_VHCADDs32 : MVE_VxCADD<"vhcadd", "s32", 0b10, 0b0>;
+
+class MVE_VADCSBC<string iname, bit I, bit subtract,
+ dag carryin, list<dag> pattern=[]>
+ : MVE_qDest_qSrc<iname, "i32", (outs MQPR:$Qd, cl_FPSCR_NZCV:$carryout),
+ !con((ins MQPR:$Qn, MQPR:$Qm), carryin),
+ "$Qd, $Qn, $Qm", vpred_r, "", pattern> {
+ bits<4> Qn;
+
+ let Inst{28} = subtract;
+ let Inst{21-20} = 0b11;
+ let Inst{19-17} = Qn{2-0};
+ let Inst{16} = 0b0;
+ let Inst{12} = I;
+ let Inst{8} = 0b1;
+ let Inst{7} = Qn{3};
+ let Inst{0} = 0b0;
+
+ // Custom decoder method in order to add the FPSCR operand(s), which
+ // Tablegen won't do right
+ let DecoderMethod = "DecodeMVEVADCInstruction";
+}
+
+def MVE_VADC : MVE_VADCSBC<"vadc", 0b0, 0b0, (ins cl_FPSCR_NZCV:$carryin)>;
+def MVE_VADCI : MVE_VADCSBC<"vadci", 0b1, 0b0, (ins)>;
+
+def MVE_VSBC : MVE_VADCSBC<"vsbc", 0b0, 0b1, (ins cl_FPSCR_NZCV:$carryin)>;
+def MVE_VSBCI : MVE_VADCSBC<"vsbci", 0b1, 0b1, (ins)>;
+
+class MVE_VQDMULL<string iname, string suffix, bit size, bit T,
+ list<dag> pattern=[]>
+ : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+ (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+ vpred_r, "", pattern> {
+ bits<4> Qn;
+
+ let Inst{28} = size;
+ let Inst{21-20} = 0b11;
+ let Inst{19-17} = Qn{2-0};
+ let Inst{16} = 0b0;
+ let Inst{12} = T;
+ let Inst{8} = 0b1;
+ let Inst{7} = Qn{3};
+ let Inst{0} = 0b1;
+}
+
+multiclass MVE_VQDMULL_halves<string suffix, bit size> {
+ def bh : MVE_VQDMULL<"vqdmullb", suffix, size, 0b0>;
+ def th : MVE_VQDMULL<"vqdmullt", suffix, size, 0b1>;
+}
+
+defm MVE_VQDMULLs16 : MVE_VQDMULL_halves<"s16", 0b0>;
+defm MVE_VQDMULLs32 : MVE_VQDMULL_halves<"s32", 0b1>;
+
+// end of mve_qDest_qSrc
+
class MVE_VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
: MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
bits<3> fc;
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=364037&r1=364036&r2=364037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Jun 21 05:13:59 2019
@@ -5966,6 +5966,7 @@ StringRef ARMAsmParser::splitMnemonic(St
Mnemonic == "vnege" || Mnemonic == "vnegt" ||
Mnemonic == "vmule" || Mnemonic == "vmult" ||
Mnemonic == "vrintne" ||
+ Mnemonic == "vcmult" || Mnemonic == "vcmule" ||
Mnemonic.startswith("vq")))) {
unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
if (CC != ~0U) {
@@ -6010,7 +6011,10 @@ StringRef ARMAsmParser::splitMnemonic(St
if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
- Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vcvt") {
+ Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" &&
+ Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" &&
+ Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" &&
+ Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
if (CC != ~0U) {
Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
@@ -6683,6 +6687,16 @@ bool ARMAsmParser::ParseInstruction(Pars
ARMOperand::CreateVPTPred(ARMVCC::Else, PLoc));
Operands.insert(Operands.begin(),
ARMOperand::CreateToken(StringRef("vcvtn"), MLoc));
+ } else if (Mnemonic == "vmul" && PredicationCode == ARMCC::LT &&
+ !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
+ // Another hack, this time to distinguish between scalar predicated vmul
+ // with 'lt' predication code and the vector instruction vmullt with
+ // vector predication code "none"
+ Operands.erase(Operands.begin() + 1);
+ Operands.erase(Operands.begin());
+ SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
+ Operands.insert(Operands.begin(),
+ ARMOperand::CreateToken(StringRef("vmullt"), MLoc));
}
// For vmov and vcmp, as mentioned earlier, we did not add the vector
// predication code, since these may contain operands that require
@@ -7541,6 +7555,31 @@ bool ARMAsmParser::validateInstruction(M
"list of registers must be at least 1 and at most 16");
break;
}
+ case ARM::MVE_VQDMULLs32bh:
+ case ARM::MVE_VQDMULLs32th:
+ case ARM::MVE_VCMULf32:
+ case ARM::MVE_VMULLs32bh:
+ case ARM::MVE_VMULLs32th:
+ case ARM::MVE_VMULLu32bh:
+ case ARM::MVE_VMULLu32th:
+ case ARM::MVE_VQDMLADHs32:
+ case ARM::MVE_VQDMLADHXs32:
+ case ARM::MVE_VQRDMLADHs32:
+ case ARM::MVE_VQRDMLADHXs32:
+ case ARM::MVE_VQDMLSDHs32:
+ case ARM::MVE_VQDMLSDHXs32:
+ case ARM::MVE_VQRDMLSDHs32:
+ case ARM::MVE_VQRDMLSDHXs32: {
+ if (Operands[3]->getReg() == Operands[4]->getReg()) {
+ return Error (Operands[3]->getStartLoc(),
+ "Qd register and Qn register can't be identical");
+ }
+ if (Operands[3]->getReg() == Operands[5]->getReg()) {
+ return Error (Operands[3]->getStartLoc(),
+ "Qd register and Qm register can't be identical");
+ }
+ break;
+ }
}
return false;
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=364037&r1=364036&r2=364037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Jun 21 05:13:59 2019
@@ -312,6 +312,8 @@ static DecodeStatus DecodeNEONModImmInst
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
@@ -3461,6 +3463,31 @@ DecodeMVEModImmInstruction(MCInst &Inst,
return S;
}
+
+static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Qd = fieldFromInstruction(Insn, 13, 3);
+ Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
+
+ unsigned Qn = fieldFromInstruction(Insn, 17, 3);
+ Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ unsigned Qm = fieldFromInstruction(Insn, 1, 3);
+ Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
+ Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
+ Inst.addOperand(MCOperand::createImm(Qd));
+
+ return S;
+}
static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
Added: llvm/trunk/test/MC/ARM/mve-qdest-qsrc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mve-qdest-qsrc.s?rev=364037&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/mve-qdest-qsrc.s (added)
+++ llvm/trunk/test/MC/ARM/mve-qdest-qsrc.s Fri Jun 21 05:13:59 2019
@@ -0,0 +1,541 @@
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \
+# RUN: | FileCheck --check-prefix=CHECK-NOFP %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
+# RUN: | FileCheck --check-prefix=CHECK %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
+
+# CHECK: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
+# CHECK-NOFP-NOT: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
+vcvtb.f16.f32 q1, q4
+
+# CHECK: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
+# CHECK-NOFP-NOT: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
+vcvtt.f32.f16 q0, q1
+
+# CHECK: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
+# CHECK-NOFP-NOT: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
+vcvtt.f64.f16 d0, s0
+
+# CHECK: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
+# CHECK-NOFP-NOT: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
+vcvtt.f16.f64 s1, d2
+
+# CHECK: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
+# CHECK-NOFP-NOT: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
+vcvtt.f16.f32 q1, q4
+
+# CHECK: vqdmladhx.s8 q1, q6, q6 @ encoding: [0x0c,0xee,0x0c,0x3e]
+# CHECK-NOFP: vqdmladhx.s8 q1, q6, q6 @ encoding: [0x0c,0xee,0x0c,0x3e]
+vqdmladhx.s8 q1, q6, q6
+
+# CHECK: vqdmladhx.s16 q0, q1, q4 @ encoding: [0x12,0xee,0x08,0x1e]
+# CHECK-NOFP: vqdmladhx.s16 q0, q1, q4 @ encoding: [0x12,0xee,0x08,0x1e]
+vqdmladhx.s16 q0, q1, q4
+
+# CHECK: vqdmladhx.s32 q0, q3, q7 @ encoding: [0x26,0xee,0x0e,0x1e]
+# CHECK-NOFP: vqdmladhx.s32 q0, q3, q7 @ encoding: [0x26,0xee,0x0e,0x1e]
+vqdmladhx.s32 q0, q3, q7
+
+# CHECK: vqdmladh.s8 q0, q1, q1 @ encoding: [0x02,0xee,0x02,0x0e]
+# CHECK-NOFP: vqdmladh.s8 q0, q1, q1 @ encoding: [0x02,0xee,0x02,0x0e]
+vqdmladh.s8 q0, q1, q1
+
+# CHECK: vqdmladh.s16 q0, q2, q2 @ encoding: [0x14,0xee,0x04,0x0e]
+# CHECK-NOFP: vqdmladh.s16 q0, q2, q2 @ encoding: [0x14,0xee,0x04,0x0e]
+vqdmladh.s16 q0, q2, q2
+
+# CHECK: vqdmladh.s32 q1, q5, q7 @ encoding: [0x2a,0xee,0x0e,0x2e]
+# CHECK-NOFP: vqdmladh.s32 q1, q5, q7 @ encoding: [0x2a,0xee,0x0e,0x2e]
+vqdmladh.s32 q1, q5, q7
+
+# CHECK: vqrdmladhx.s8 q0, q7, q0 @ encoding: [0x0e,0xee,0x01,0x1e]
+# CHECK-NOFP: vqrdmladhx.s8 q0, q7, q0 @ encoding: [0x0e,0xee,0x01,0x1e]
+vqrdmladhx.s8 q0, q7, q0
+
+# CHECK: vqrdmladhx.s16 q0, q0, q1 @ encoding: [0x10,0xee,0x03,0x1e]
+# CHECK-NOFP: vqrdmladhx.s16 q0, q0, q1 @ encoding: [0x10,0xee,0x03,0x1e]
+vqrdmladhx.s16 q0, q0, q1
+
+# CHECK: vqrdmladhx.s32 q1, q0, q4 @ encoding: [0x20,0xee,0x09,0x3e]
+# CHECK-NOFP: vqrdmladhx.s32 q1, q0, q4 @ encoding: [0x20,0xee,0x09,0x3e]
+vqrdmladhx.s32 q1, q0, q4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vqrdmladhx.s32 q1, q1, q0
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vqrdmladhx.s32 q1, q0, q1
+
+# CHECK: vqrdmladh.s8 q0, q6, q2 @ encoding: [0x0c,0xee,0x05,0x0e]
+# CHECK-NOFP: vqrdmladh.s8 q0, q6, q2 @ encoding: [0x0c,0xee,0x05,0x0e]
+vqrdmladh.s8 q0, q6, q2
+
+# CHECK: vqrdmladh.s16 q1, q5, q4 @ encoding: [0x1a,0xee,0x09,0x2e]
+# CHECK-NOFP: vqrdmladh.s16 q1, q5, q4 @ encoding: [0x1a,0xee,0x09,0x2e]
+vqrdmladh.s16 q1, q5, q4
+
+# CHECK: vqrdmladh.s32 q0, q2, q2 @ encoding: [0x24,0xee,0x05,0x0e]
+# CHECK-NOFP: vqrdmladh.s32 q0, q2, q2 @ encoding: [0x24,0xee,0x05,0x0e]
+vqrdmladh.s32 q0, q2, q2
+
+# CHECK: vqdmlsdhx.s8 q1, q4, q7 @ encoding: [0x08,0xfe,0x0e,0x3e]
+# CHECK-NOFP: vqdmlsdhx.s8 q1, q4, q7 @ encoding: [0x08,0xfe,0x0e,0x3e]
+vqdmlsdhx.s8 q1, q4, q7
+
+# CHECK: vqdmlsdhx.s16 q0, q2, q5 @ encoding: [0x14,0xfe,0x0a,0x1e]
+# CHECK-NOFP: vqdmlsdhx.s16 q0, q2, q5 @ encoding: [0x14,0xfe,0x0a,0x1e]
+vqdmlsdhx.s16 q0, q2, q5
+
+# CHECK: vqdmlsdhx.s32 q3, q4, q6 @ encoding: [0x28,0xfe,0x0c,0x7e]
+# CHECK-NOFP: vqdmlsdhx.s32 q3, q4, q6 @ encoding: [0x28,0xfe,0x0c,0x7e]
+vqdmlsdhx.s32 q3, q4, q6
+
+# CHECK: vqdmlsdh.s8 q0, q3, q6 @ encoding: [0x06,0xfe,0x0c,0x0e]
+# CHECK-NOFP: vqdmlsdh.s8 q0, q3, q6 @ encoding: [0x06,0xfe,0x0c,0x0e]
+vqdmlsdh.s8 q0, q3, q6
+
+# CHECK: vqdmlsdh.s16 q0, q4, q1 @ encoding: [0x18,0xfe,0x02,0x0e]
+# CHECK-NOFP: vqdmlsdh.s16 q0, q4, q1 @ encoding: [0x18,0xfe,0x02,0x0e]
+vqdmlsdh.s16 q0, q4, q1
+
+# CHECK: vqdmlsdh.s32 q2, q5, q0 @ encoding: [0x2a,0xfe,0x00,0x4e]
+# CHECK-NOFP: vqdmlsdh.s32 q2, q5, q0 @ encoding: [0x2a,0xfe,0x00,0x4e]
+vqdmlsdh.s32 q2, q5, q0
+
+# CHECK: vqrdmlsdhx.s8 q0, q3, q1 @ encoding: [0x06,0xfe,0x03,0x1e]
+# CHECK-NOFP: vqrdmlsdhx.s8 q0, q3, q1 @ encoding: [0x06,0xfe,0x03,0x1e]
+vqrdmlsdhx.s8 q0, q3, q1
+
+# CHECK: vqrdmlsdhx.s16 q0, q1, q4 @ encoding: [0x12,0xfe,0x09,0x1e]
+# CHECK-NOFP: vqrdmlsdhx.s16 q0, q1, q4 @ encoding: [0x12,0xfe,0x09,0x1e]
+vqrdmlsdhx.s16 q0, q1, q4
+
+# CHECK: vqrdmlsdhx.s32 q1, q6, q3 @ encoding: [0x2c,0xfe,0x07,0x3e]
+# CHECK-NOFP: vqrdmlsdhx.s32 q1, q6, q3 @ encoding: [0x2c,0xfe,0x07,0x3e]
+vqrdmlsdhx.s32 q1, q6, q3
+
+# CHECK: vqrdmlsdh.s8 q3, q3, q0 @ encoding: [0x06,0xfe,0x01,0x6e]
+# CHECK-NOFP: vqrdmlsdh.s8 q3, q3, q0 @ encoding: [0x06,0xfe,0x01,0x6e]
+vqrdmlsdh.s8 q3, q3, q0
+
+# CHECK: vqrdmlsdh.s16 q0, q7, q4 @ encoding: [0x1e,0xfe,0x09,0x0e]
+# CHECK-NOFP: vqrdmlsdh.s16 q0, q7, q4 @ encoding: [0x1e,0xfe,0x09,0x0e]
+vqrdmlsdh.s16 q0, q7, q4
+
+# CHECK: vqrdmlsdh.s32 q0, q6, q7 @ encoding: [0x2c,0xfe,0x0f,0x0e]
+# CHECK-NOFP: vqrdmlsdh.s32 q0, q6, q7 @ encoding: [0x2c,0xfe,0x0f,0x0e]
+vqrdmlsdh.s32 q0, q6, q7
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vqrdmlsdh.s32 q0, q0, q7
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vqrdmlsdh.s32 q0, q6, q0
+
+# CHECK: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]
+# CHECK-NOFP-NOT: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]
+vcmul.f16 q0, q1, q2, #90
+
+# CHECK: vcmul.f16 q6, q2, q5, #0 @ encoding: [0x34,0xee,0x0a,0xce]
+# CHECK-NOFP-NOT: vcmul.f16 q6, q2, q5, #0 @ encoding: [0x34,0xee,0x0a,0xce]
+vcmul.f16 q6, q2, q5, #0
+
+# CHECK: vcmul.f16 q1, q0, q5, #90 @ encoding: [0x30,0xee,0x0b,0x2e]
+# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #90 @ encoding: [0x30,0xee,0x0b,0x2e]
+vcmul.f16 q1, q0, q5, #90
+
+# CHECK: vcmul.f16 q1, q0, q5, #180 @ encoding: [0x30,0xee,0x0a,0x3e]
+# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #180 @ encoding: [0x30,0xee,0x0a,0x3e]
+vcmul.f16 q1, q0, q5, #180
+
+# CHECK: vcmul.f16 q1, q0, q5, #270 @ encoding: [0x30,0xee,0x0b,0x3e]
+# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #270 @ encoding: [0x30,0xee,0x0b,0x3e]
+vcmul.f16 q1, q0, q5, #270
+
+# CHECK: vcmul.f16 q1, q0, q1, #270 @ encoding: [0x30,0xee,0x03,0x3e]
+# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q1, #270 @ encoding: [0x30,0xee,0x03,0x3e]
+vcmul.f16 q1, q0, q1, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 0, 90, 180 or 270
+vcmul.f16 q1, q0, q5, #300
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vcmul.f32 q1, q1, q5, #0
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vcmul.f32 q1, q5, q1, #0
+
+# CHECK: vcmul.f32 q1, q7, q5, #0 @ encoding: [0x3e,0xfe,0x0a,0x2e]
+# CHECK-NOFP-NOT: vcmul.f32 q1, q7, q5, #0 @ encoding: [0x3e,0xfe,0x0a,0x2e]
+vcmul.f32 q1, q7, q5, #0
+
+# CHECK: vcmul.f32 q3, q4, q2, #90 @ encoding: [0x38,0xfe,0x05,0x6e]
+# CHECK-NOFP-NOT: vcmul.f32 q3, q4, q2, #90 @ encoding: [0x38,0xfe,0x05,0x6e]
+vcmul.f32 q3, q4, q2, #90
+
+# CHECK: vcmul.f32 q5, q1, q3, #180 @ encoding: [0x32,0xfe,0x06,0xbe]
+# CHECK-NOFP-NOT: vcmul.f32 q5, q1, q3, #180 @ encoding: [0x32,0xfe,0x06,0xbe]
+vcmul.f32 q5, q1, q3, #180
+
+# CHECK: vcmul.f32 q0, q7, q4, #270 @ encoding: [0x3e,0xfe,0x09,0x1e]
+# CHECK-NOFP-NOT: vcmul.f32 q0, q7, q4, #270 @ encoding: [0x3e,0xfe,0x09,0x1e]
+vcmul.f32 q0, q7, q4, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 0, 90, 180 or 270
+vcmul.f32 q1, q0, q5, #300
+
+# CHECK: vmullb.s8 q2, q6, q0 @ encoding: [0x0d,0xee,0x00,0x4e]
+# CHECK-NOFP: vmullb.s8 q2, q6, q0 @ encoding: [0x0d,0xee,0x00,0x4e]
+vmullb.s8 q2, q6, q0
+
+# CHECK: vmullb.s16 q3, q4, q3 @ encoding: [0x19,0xee,0x06,0x6e]
+# CHECK-NOFP: vmullb.s16 q3, q4, q3 @ encoding: [0x19,0xee,0x06,0x6e]
+vmullb.s16 q3, q4, q3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vmullb.s32 q3, q4, q3
+
+# CHECK: vmullb.s32 q3, q5, q6 @ encoding: [0x2b,0xee,0x0c,0x6e]
+# CHECK-NOFP: vmullb.s32 q3, q5, q6 @ encoding: [0x2b,0xee,0x0c,0x6e]
+vmullb.s32 q3, q5, q6
+
+# CHECK: vmullt.s8 q0, q6, q2 @ encoding: [0x0d,0xee,0x04,0x1e]
+# CHECK-NOFP: vmullt.s8 q0, q6, q2 @ encoding: [0x0d,0xee,0x04,0x1e]
+vmullt.s8 q0, q6, q2
+
+# CHECK: vmullt.s16 q0, q0, q2 @ encoding: [0x11,0xee,0x04,0x1e]
+# CHECK-NOFP: vmullt.s16 q0, q0, q2 @ encoding: [0x11,0xee,0x04,0x1e]
+vmullt.s16 q0, q0, q2
+
+# CHECK: vmullt.s32 q2, q4, q4 @ encoding: [0x29,0xee,0x08,0x5e]
+# CHECK-NOFP: vmullt.s32 q2, q4, q4 @ encoding: [0x29,0xee,0x08,0x5e]
+vmullt.s32 q2, q4, q4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vmullt.s32 q4, q4, q2
+
+# CHECK: vmullb.p8 q2, q3, q7 @ encoding: [0x37,0xee,0x0e,0x4e]
+# CHECK-NOFP: vmullb.p8 q2, q3, q7 @ encoding: [0x37,0xee,0x0e,0x4e]
+vmullb.p8 q2, q3, q7
+
+# CHECK: vmullb.p16 q0, q1, q3 @ encoding: [0x33,0xfe,0x06,0x0e]
+# CHECK-NOFP: vmullb.p16 q0, q1, q3 @ encoding: [0x33,0xfe,0x06,0x0e]
+vmullb.p16 q0, q1, q3
+
+# CHECK: vmullt.p8 q1, q1, q7 @ encoding: [0x33,0xee,0x0e,0x3e]
+# CHECK-NOFP: vmullt.p8 q1, q1, q7 @ encoding: [0x33,0xee,0x0e,0x3e]
+vmullt.p8 q1, q1, q7
+
+# CHECK: vmullt.p16 q0, q7, q7 @ encoding: [0x3f,0xfe,0x0e,0x1e]
+# CHECK-NOFP: vmullt.p16 q0, q7, q7 @ encoding: [0x3f,0xfe,0x0e,0x1e]
+vmullt.p16 q0, q7, q7
+
+# CHECK: vmulh.s8 q0, q4, q5 @ encoding: [0x09,0xee,0x0b,0x0e]
+# CHECK-NOFP: vmulh.s8 q0, q4, q5 @ encoding: [0x09,0xee,0x0b,0x0e]
+vmulh.s8 q0, q4, q5
+
+# CHECK: vmulh.s16 q0, q7, q4 @ encoding: [0x1f,0xee,0x09,0x0e]
+# CHECK-NOFP: vmulh.s16 q0, q7, q4 @ encoding: [0x1f,0xee,0x09,0x0e]
+vmulh.s16 q0, q7, q4
+
+# CHECK: vmulh.s32 q0, q7, q4 @ encoding: [0x2f,0xee,0x09,0x0e]
+# CHECK-NOFP: vmulh.s32 q0, q7, q4 @ encoding: [0x2f,0xee,0x09,0x0e]
+vmulh.s32 q0, q7, q4
+
+# CHECK: vmulh.u8 q3, q5, q2 @ encoding: [0x0b,0xfe,0x05,0x6e]
+# CHECK-NOFP: vmulh.u8 q3, q5, q2 @ encoding: [0x0b,0xfe,0x05,0x6e]
+vmulh.u8 q3, q5, q2
+
+# CHECK: vmulh.u16 q2, q7, q4 @ encoding: [0x1f,0xfe,0x09,0x4e]
+# CHECK-NOFP: vmulh.u16 q2, q7, q4 @ encoding: [0x1f,0xfe,0x09,0x4e]
+vmulh.u16 q2, q7, q4
+
+# CHECK: vmulh.u32 q1, q3, q2 @ encoding: [0x27,0xfe,0x05,0x2e]
+# CHECK-NOFP: vmulh.u32 q1, q3, q2 @ encoding: [0x27,0xfe,0x05,0x2e]
+vmulh.u32 q1, q3, q2
+
+# CHECK: vrmulh.s8 q1, q1, q2 @ encoding: [0x03,0xee,0x05,0x3e]
+# CHECK-NOFP: vrmulh.s8 q1, q1, q2 @ encoding: [0x03,0xee,0x05,0x3e]
+vrmulh.s8 q1, q1, q2
+
+# CHECK: vrmulh.s16 q1, q1, q2 @ encoding: [0x13,0xee,0x05,0x3e]
+# CHECK-NOFP: vrmulh.s16 q1, q1, q2 @ encoding: [0x13,0xee,0x05,0x3e]
+vrmulh.s16 q1, q1, q2
+
+# CHECK: vrmulh.s32 q3, q1, q0 @ encoding: [0x23,0xee,0x01,0x7e]
+# CHECK-NOFP: vrmulh.s32 q3, q1, q0 @ encoding: [0x23,0xee,0x01,0x7e]
+vrmulh.s32 q3, q1, q0
+
+# CHECK: vrmulh.u8 q1, q6, q0 @ encoding: [0x0d,0xfe,0x01,0x3e]
+# CHECK-NOFP: vrmulh.u8 q1, q6, q0 @ encoding: [0x0d,0xfe,0x01,0x3e]
+vrmulh.u8 q1, q6, q0
+
+# CHECK: vrmulh.u16 q4, q3, q6 @ encoding: [0x17,0xfe,0x0d,0x9e]
+# CHECK-NOFP: vrmulh.u16 q4, q3, q6 @ encoding: [0x17,0xfe,0x0d,0x9e]
+vrmulh.u16 q4, q3, q6
+
+# CHECK: vrmulh.u32 q1, q2, q2 @ encoding: [0x25,0xfe,0x05,0x3e]
+# CHECK-NOFP: vrmulh.u32 q1, q2, q2 @ encoding: [0x25,0xfe,0x05,0x3e]
+vrmulh.u32 q1, q2, q2
+
+# CHECK: vqmovnb.s16 q0, q1 @ encoding: [0x33,0xee,0x03,0x0e]
+# CHECK-NOFP: vqmovnb.s16 q0, q1 @ encoding: [0x33,0xee,0x03,0x0e]
+vqmovnb.s16 q0, q1
+
+# CHECK: vqmovnt.s16 q2, q0 @ encoding: [0x33,0xee,0x01,0x5e]
+# CHECK-NOFP: vqmovnt.s16 q2, q0 @ encoding: [0x33,0xee,0x01,0x5e]
+vqmovnt.s16 q2, q0
+
+# CHECK: vqmovnb.s32 q0, q5 @ encoding: [0x37,0xee,0x0b,0x0e]
+# CHECK-NOFP: vqmovnb.s32 q0, q5 @ encoding: [0x37,0xee,0x0b,0x0e]
+vqmovnb.s32 q0, q5
+
+# CHECK: vqmovnt.s32 q0, q1 @ encoding: [0x37,0xee,0x03,0x1e]
+# CHECK-NOFP: vqmovnt.s32 q0, q1 @ encoding: [0x37,0xee,0x03,0x1e]
+vqmovnt.s32 q0, q1
+
+# CHECK: vqmovnb.u16 q0, q4 @ encoding: [0x33,0xfe,0x09,0x0e]
+# CHECK-NOFP: vqmovnb.u16 q0, q4 @ encoding: [0x33,0xfe,0x09,0x0e]
+vqmovnb.u16 q0, q4
+
+# CHECK: vqmovnt.u16 q0, q7 @ encoding: [0x33,0xfe,0x0f,0x1e]
+# CHECK-NOFP: vqmovnt.u16 q0, q7 @ encoding: [0x33,0xfe,0x0f,0x1e]
+vqmovnt.u16 q0, q7
+
+# CHECK: vqmovnb.u32 q0, q4 @ encoding: [0x37,0xfe,0x09,0x0e]
+# CHECK-NOFP: vqmovnb.u32 q0, q4 @ encoding: [0x37,0xfe,0x09,0x0e]
+vqmovnb.u32 q0, q4
+
+# CHECK: vqmovnt.u32 q0, q2 @ encoding: [0x37,0xfe,0x05,0x1e]
+# CHECK-NOFP: vqmovnt.u32 q0, q2 @ encoding: [0x37,0xfe,0x05,0x1e]
+vqmovnt.u32 q0, q2
+
+# CHECK: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
+# CHECK-NOFP-NOT: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
+vcvtb.f16.f32 q1, q4
+
+# CHECK: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
+# CHECK-NOFP-NOT: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
+vcvtt.f16.f32 q1, q4
+
+# CHECK: vcvtb.f32.f16 q0, q3 @ encoding: [0x3f,0xfe,0x07,0x0e]
+# CHECK-NOFP-NOT: vcvtb.f32.f16 q0, q3 @ encoding: [0x3f,0xfe,0x07,0x0e]
+vcvtb.f32.f16 q0, q3
+
+# CHECK: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
+# CHECK-NOFP-NOT: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
+vcvtt.f32.f16 q0, q1
+
+# CHECK: vqmovunb.s16 q0, q3 @ encoding: [0x31,0xee,0x87,0x0e]
+# CHECK-NOFP: vqmovunb.s16 q0, q3 @ encoding: [0x31,0xee,0x87,0x0e]
+vqmovunb.s16 q0, q3
+
+# CHECK: vqmovunt.s16 q4, q1 @ encoding: [0x31,0xee,0x83,0x9e]
+# CHECK-NOFP: vqmovunt.s16 q4, q1 @ encoding: [0x31,0xee,0x83,0x9e]
+vqmovunt.s16 q4, q1
+
+# CHECK: vqmovunb.s32 q1, q7 @ encoding: [0x35,0xee,0x8f,0x2e]
+# CHECK-NOFP: vqmovunb.s32 q1, q7 @ encoding: [0x35,0xee,0x8f,0x2e]
+vqmovunb.s32 q1, q7
+
+# CHECK: vqmovunt.s32 q0, q2 @ encoding: [0x35,0xee,0x85,0x1e]
+# CHECK-NOFP: vqmovunt.s32 q0, q2 @ encoding: [0x35,0xee,0x85,0x1e]
+vqmovunt.s32 q0, q2
+
+# CHECK: vmovnb.i16 q1, q5 @ encoding: [0x31,0xfe,0x8b,0x2e]
+# CHECK-NOFP: vmovnb.i16 q1, q5 @ encoding: [0x31,0xfe,0x8b,0x2e]
+vmovnb.i16 q1, q5
+
+# CHECK: vmovnt.i16 q0, q0 @ encoding: [0x31,0xfe,0x81,0x1e]
+# CHECK-NOFP: vmovnt.i16 q0, q0 @ encoding: [0x31,0xfe,0x81,0x1e]
+vmovnt.i16 q0, q0
+
+# CHECK: vmovnb.i32 q1, q0 @ encoding: [0x35,0xfe,0x81,0x2e]
+# CHECK-NOFP: vmovnb.i32 q1, q0 @ encoding: [0x35,0xfe,0x81,0x2e]
+vmovnb.i32 q1, q0
+
+# CHECK: vmovnt.i32 q3, q3 @ encoding: [0x35,0xfe,0x87,0x7e]
+# CHECK-NOFP: vmovnt.i32 q3, q3 @ encoding: [0x35,0xfe,0x87,0x7e]
+vmovnt.i32 q3, q3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
+vhcadd.s8 q3, q7, q5, #0
+
+# CHECK: vhcadd.s8 q3, q7, q5, #90 @ encoding: [0x0e,0xee,0x0a,0x6f]
+# CHECK-NOFP: vhcadd.s8 q3, q7, q5, #90 @ encoding: [0x0e,0xee,0x0a,0x6f]
+vhcadd.s8 q3, q7, q5, #90
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
+vhcadd.s8 q3, q7, q5, #0
+
+# CHECK: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
+# CHECK-NOFP: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
+vhcadd.s16 q0, q0, q6, #90
+
+# CHECK: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
+# CHECK-NOFP: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
+vhcadd.s16 q0, q0, q6, #90
+
+# CHECK: vhcadd.s16 q3, q1, q0, #270 @ encoding: [0x12,0xee,0x00,0x7f]
+# CHECK-NOFP: vhcadd.s16 q3, q1, q0, #270 @ encoding: [0x12,0xee,0x00,0x7f]
+vhcadd.s16 q3, q1, q0, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
+vhcadd.s32 q3, q4, q5, #0
+
+# CHECK: vhcadd.s32 q3, q4, q5, #90 @ encoding: [0x28,0xee,0x0a,0x6f]
+# CHECK-NOFP: vhcadd.s32 q3, q4, q5, #90 @ encoding: [0x28,0xee,0x0a,0x6f]
+vhcadd.s32 q3, q4, q5, #90
+
+# CHECK: vhcadd.s32 q6, q7, q2, #270 @ encoding: [0x2e,0xee,0x04,0xdf]
+# CHECK-NOFP: vhcadd.s32 q6, q7, q2, #270 @ encoding: [0x2e,0xee,0x04,0xdf]
+vhcadd.s32 q6, q7, q2, #270
+
+# CHECK: vadc.i32 q1, q0, q2 @ encoding: [0x30,0xee,0x04,0x2f]
+# CHECK-NOFP: vadc.i32 q1, q0, q2 @ encoding: [0x30,0xee,0x04,0x2f]
+vadc.i32 q1, q0, q2
+
+# CHECK: vadci.i32 q0, q1, q1 @ encoding: [0x32,0xee,0x02,0x1f]
+# CHECK-NOFP: vadci.i32 q0, q1, q1 @ encoding: [0x32,0xee,0x02,0x1f]
+vadci.i32 q0, q1, q1
+
+# CHECK: vcadd.i8 q1, q0, q2, #90 @ encoding: [0x00,0xfe,0x04,0x2f]
+# CHECK-NOFP: vcadd.i8 q1, q0, q2, #90 @ encoding: [0x00,0xfe,0x04,0x2f]
+vcadd.i8 q1, q0, q2, #90
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
+vcadd.i8 q1, q0, q2, #0
+
+# CHECK: vcadd.i16 q0, q2, q3, #90 @ encoding: [0x14,0xfe,0x06,0x0f]
+# CHECK-NOFP: vcadd.i16 q0, q2, q3, #90 @ encoding: [0x14,0xfe,0x06,0x0f]
+vcadd.i16 q0, q2, q3, #90
+
+# CHECK: vcadd.i16 q0, q5, q5, #270 @ encoding: [0x1a,0xfe,0x0a,0x1f]
+# CHECK-NOFP: vcadd.i16 q0, q5, q5, #270 @ encoding: [0x1a,0xfe,0x0a,0x1f]
+vcadd.i16 q0, q5, q5, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
+vcadd.i16 q1, q0, q2, #0
+
+# CHECK: vcadd.i32 q4, q2, q5, #90 @ encoding: [0x24,0xfe,0x0a,0x8f]
+# CHECK-NOFP: vcadd.i32 q4, q2, q5, #90 @ encoding: [0x24,0xfe,0x0a,0x8f]
+vcadd.i32 q4, q2, q5, #90
+
+# CHECK: vcadd.i32 q5, q5, q0, #270 @ encoding: [0x2a,0xfe,0x00,0xbf]
+# CHECK-NOFP: vcadd.i32 q5, q5, q0, #270 @ encoding: [0x2a,0xfe,0x00,0xbf]
+vcadd.i32 q5, q5, q0, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
+vcadd.i32 q4, q2, q5, #0
+
+# CHECK: vsbc.i32 q3, q1, q1 @ encoding: [0x32,0xfe,0x02,0x6f]
+# CHECK-NOFP: vsbc.i32 q3, q1, q1 @ encoding: [0x32,0xfe,0x02,0x6f]
+vsbc.i32 q3, q1, q1
+
+# CHECK: vsbci.i32 q2, q6, q2 @ encoding: [0x3c,0xfe,0x04,0x5f]
+# CHECK-NOFP: vsbci.i32 q2, q6, q2 @ encoding: [0x3c,0xfe,0x04,0x5f]
+vsbci.i32 q2, q6, q2
+
+# CHECK: vqdmullb.s16 q0, q4, q5 @ encoding: [0x38,0xee,0x0b,0x0f]
+# CHECK-NOFP: vqdmullb.s16 q0, q4, q5 @ encoding: [0x38,0xee,0x0b,0x0f]
+vqdmullb.s16 q0, q4, q5
+
+# CHECK: vqdmullt.s16 q0, q6, q5 @ encoding: [0x3c,0xee,0x0b,0x1f]
+# CHECK-NOFP: vqdmullt.s16 q0, q6, q5 @ encoding: [0x3c,0xee,0x0b,0x1f]
+vqdmullt.s16 q0, q6, q5
+
+# CHECK: vqdmullb.s32 q0, q3, q7 @ encoding: [0x36,0xfe,0x0f,0x0f]
+# CHECK-NOFP: vqdmullb.s32 q0, q3, q7 @ encoding: [0x36,0xfe,0x0f,0x0f]
+vqdmullb.s32 q0, q3, q7
+
+# CHECK: vqdmullt.s32 q0, q7, q5 @ encoding: [0x3e,0xfe,0x0b,0x1f]
+# CHECK-NOFP: vqdmullt.s32 q0, q7, q5 @ encoding: [0x3e,0xfe,0x0b,0x1f]
+vqdmullt.s32 q0, q7, q5
+
+# CHECK: vqdmullb.s16 q0, q1, q0 @ encoding: [0x32,0xee,0x01,0x0f]
+# CHECK-NOFP: vqdmullb.s16 q0, q1, q0 @ encoding: [0x32,0xee,0x01,0x0f]
+vqdmullb.s16 q0, q1, q0
+
+# CHECK: vqdmullt.s16 q0, q0, q5 @ encoding: [0x30,0xee,0x0b,0x1f]
+# CHECK-NOFP: vqdmullt.s16 q0, q0, q5 @ encoding: [0x30,0xee,0x0b,0x1f]
+vqdmullt.s16 q0, q0, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vqdmullb.s32 q0, q1, q0
+
+vqdmullt.s16 q0, q1, q2
+# CHECK: vqdmullt.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x1f]
+# CHECK-NOFP: vqdmullt.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x1f]
+
+vpste
+vqdmulltt.s32 q0, q1, q2
+vqdmullbe.s16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vqdmulltt.s32 q0, q1, q2 @ encoding: [0x32,0xfe,0x05,0x1f]
+# CHECK-NOFP: vqdmulltt.s32 q0, q1, q2 @ encoding: [0x32,0xfe,0x05,0x1f]
+# CHECK: vqdmullbe.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x0f]
+# CHECK-NOFP: vqdmullbe.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x0f]
+
+vpste
+vmulltt.p8 q0, q1, q2
+vmullbe.p16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vmulltt.p8 q0, q1, q2 @ encoding: [0x33,0xee,0x04,0x1e]
+# CHECK-NOFP: vmulltt.p8 q0, q1, q2 @ encoding: [0x33,0xee,0x04,0x1e]
+# CHECK: vmullbe.p16 q0, q1, q2 @ encoding: [0x33,0xfe,0x04,0x0e]
+# CHECK-NOFP: vmullbe.p16 q0, q1, q2 @ encoding: [0x33,0xfe,0x04,0x0e]
+
+# ----------------------------------------------------------------------
+# The following tests have to go last because of the NOFP-NOT checks inside the
+# VPT block.
+
+vpste
+vcmult.f16 q0, q1, q2, #180
+vcmule.f16 q0, q1, q2, #180
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vcmult.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
+# CHECK-NOFP-NOT: vcmult.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
+# CHECK: vcmule.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
+# CHECK-NOFP-NOT: vcmule.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
+
+vpstet
+vcvtbt.f16.f32 q0, q1
+vcvtne.s16.f16 q0, q1
+vcvtmt.s16.f16 q0, q1
+# CHECK: vpstet @ encoding: [0x71,0xfe,0x4d,0xcf]
+# CHECK: vcvtbt.f16.f32 q0, q1 @ encoding: [0x3f,0xee,0x03,0x0e]
+# CHECK-NOFP-NOT: vcvtbt.f16.f32 q0, q1 @ encoding: [0x3f,0xee,0x03,0x0e]
+# CHECK: vcvtne.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x01]
+# CHECK-NOFP-NOT: vcvtne.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x01]
+# CHECK: vcvtmt.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x03
+# CHECK-NOFP-NOT: vcvtmt.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x03
+
+vpte.f32 lt, q3, r1
+vcvttt.f16.f32 q2, q0
+vcvtte.f32.f16 q1, q0
+# CHECK: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xc1,0x9f]
+# CHECK-NOFP-NOT: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xe1,0x8f]
+# CHECK: vcvttt.f16.f32 q2, q0 @ encoding: [0x3f,0xee,0x01,0x5e]
+# CHECK-NOFP-NOT: vcvttt.f16.f32 q2, q0 @ encoding: [0x3f,0xee,0x01,0x5e]
+# CHECK: vcvtte.f32.f16 q1, q0 @ encoding: [0x3f,0xfe,0x01,0x3e]
+
+vpte.f32 lt, q3, r1
+vcvtbt.f16.f32 q2, q0
+vcvtbe.f32.f16 q1, q0
+# CHECK: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xc1,0x9f]
+# CHECK-NOFP-NOT: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xe1,0x8f]
+# CHECK: vcvtbt.f16.f32 q2, q0 @ encoding: [0x3f,0xee,0x01,0x4e]
+# CHECK-NOFP-NOT: vcvtbt.f16.f32 q2, q0 @ encoding: [0x3f,0xee,0x01,0x4e]
+# CHECK: vcvtbe.f32.f16 q1, q0 @ encoding: [0x3f,0xfe,0x01,0x2e]
+# CHECK-NOFP-NOT: vcvtbe.f32.f16 q1, q0 @ encoding: [0x3f,0xfe,0x01,0x2e]
+
+ite eq
+vcvtteq.f16.f32 s0, s1
+vcvttne.f16.f32 s0, s1
+# CHECK: ite eq @ encoding: [0x0c,0xbf]
+# CHECK: vcvtteq.f16.f32 s0, s1 @ encoding: [0xb3,0xee,0xe0,0x0a]
+# CHECK-NOFP-NOT: vcvtteq.f16.f32 s0, s1 @ encoding: [0xb3,0xee,0xe0,0x0a]
+# CHECK: vcvttne.f16.f32 s0, s1 @ encoding: [0xb3,0xee,0xe0,0x0a]
+# CHECK-NOFP-NOT: vcvttne.f16.f32 s0, s1 @ encoding: [0xb3,0xee,0xe0,0x0a]
Propchange: llvm/trunk/test/MC/ARM/mve-qdest-qsrc.s
------------------------------------------------------------------------------
svn:eol-style = native
Propchange: llvm/trunk/test/MC/ARM/mve-qdest-qsrc.s
------------------------------------------------------------------------------
svn:keywords = Rev Date Author URL Id
Added: llvm/trunk/test/MC/Disassembler/ARM/mve-qdest-qsrc.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/mve-qdest-qsrc.txt?rev=364037&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/mve-qdest-qsrc.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/mve-qdest-qsrc.txt Fri Jun 21 05:13:59 2019
@@ -0,0 +1,391 @@
+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
+# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
+
+# CHECK: vqdmladhx.s8 q1, q6, q6 @ encoding: [0x0c,0xee,0x0c,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xee,0x0c,0x3e]
+
+# CHECK: vqdmladhx.s16 q0, q1, q4 @ encoding: [0x12,0xee,0x08,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xee,0x08,0x1e]
+
+# CHECK: vqdmladhx.s32 q0, q3, q7 @ encoding: [0x26,0xee,0x0e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xee,0x0e,0x1e]
+
+# CHECK: vqdmladh.s8 q0, q1, q1 @ encoding: [0x02,0xee,0x02,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xee,0x02,0x0e]
+
+# CHECK: vqdmladh.s16 q0, q2, q2 @ encoding: [0x14,0xee,0x04,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xee,0x04,0x0e]
+
+# CHECK: vqdmladh.s32 q1, q5, q7 @ encoding: [0x2a,0xee,0x0e,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xee,0x0e,0x2e]
+
+# CHECK: vqrdmladhx.s8 q0, q7, q0 @ encoding: [0x0e,0xee,0x01,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0e,0xee,0x01,0x1e]
+
+# CHECK: vqrdmladhx.s16 q0, q0, q1 @ encoding: [0x10,0xee,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xee,0x03,0x1e]
+
+# CHECK: vqrdmladhx.s32 q1, q0, q4 @ encoding: [0x20,0xee,0x09,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xee,0x09,0x3e]
+
+# CHECK: vqrdmladh.s8 q0, q6, q2 @ encoding: [0x0c,0xee,0x05,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xee,0x05,0x0e]
+
+# CHECK: vqrdmladh.s16 q1, q5, q4 @ encoding: [0x1a,0xee,0x09,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xee,0x09,0x2e]
+
+# CHECK: vqrdmladh.s32 q0, q2, q2 @ encoding: [0x24,0xee,0x05,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xee,0x05,0x0e]
+
+# CHECK: vqdmlsdhx.s8 q1, q4, q7 @ encoding: [0x08,0xfe,0x0e,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xfe,0x0e,0x3e]
+
+# CHECK: vqdmlsdhx.s16 q0, q2, q5 @ encoding: [0x14,0xfe,0x0a,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xfe,0x0a,0x1e]
+
+# CHECK: vqdmlsdhx.s32 q3, q4, q6 @ encoding: [0x28,0xfe,0x0c,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xfe,0x0c,0x7e]
+
+# CHECK: vqdmlsdh.s8 q0, q3, q6 @ encoding: [0x06,0xfe,0x0c,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xfe,0x0c,0x0e]
+
+# CHECK: vqdmlsdh.s16 q0, q4, q1 @ encoding: [0x18,0xfe,0x02,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xfe,0x02,0x0e]
+
+# CHECK: vqdmlsdh.s32 q2, q5, q0 @ encoding: [0x2a,0xfe,0x00,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xfe,0x00,0x4e]
+
+# CHECK: vqrdmlsdhx.s8 q0, q3, q1 @ encoding: [0x06,0xfe,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xfe,0x03,0x1e]
+
+# CHECK: vqrdmlsdhx.s16 q0, q1, q4 @ encoding: [0x12,0xfe,0x09,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xfe,0x09,0x1e]
+
+# CHECK: vqrdmlsdhx.s32 q1, q6, q3 @ encoding: [0x2c,0xfe,0x07,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2c,0xfe,0x07,0x3e]
+
+# CHECK: vqrdmlsdh.s8 q3, q3, q0 @ encoding: [0x06,0xfe,0x01,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xfe,0x01,0x6e]
+
+# CHECK: vqrdmlsdh.s16 q0, q7, q4 @ encoding: [0x1e,0xfe,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xfe,0x09,0x0e]
+
+# CHECK: vqrdmlsdh.s32 q0, q6, q7 @ encoding: [0x2c,0xfe,0x0f,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2c,0xfe,0x0f,0x0e]
+
+# CHECK: vcmul.f16 q6, q2, q5, #0 @ encoding: [0x34,0xee,0x0a,0xce]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x34,0xee,0x0a,0xce]
+
+# CHECK: vcmul.f16 q1, q0, q5, #90 @ encoding: [0x30,0xee,0x0b,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xee,0x0b,0x2e]
+
+# CHECK: vcmul.f16 q1, q0, q5, #180 @ encoding: [0x30,0xee,0x0a,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xee,0x0a,0x3e]
+
+# CHECK: vcmul.f16 q1, q0, q5, #270 @ encoding: [0x30,0xee,0x0b,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xee,0x0b,0x3e]
+
+# CHECK: vcmul.f32 q1, q7, q5, #0 @ encoding: [0x3e,0xfe,0x0a,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3e,0xfe,0x0a,0x2e]
+
+# CHECK: vcmul.f32 q3, q4, q2, #90 @ encoding: [0x38,0xfe,0x05,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x38,0xfe,0x05,0x6e]
+
+# CHECK: vcmul.f32 q5, q1, q3, #180 @ encoding: [0x32,0xfe,0x06,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xfe,0x06,0xbe]
+
+# CHECK: vcmul.f32 q0, q7, q4, #270 @ encoding: [0x3e,0xfe,0x09,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3e,0xfe,0x09,0x1e]
+
+# CHECK: vmullb.s8 q2, q6, q0 @ encoding: [0x0d,0xee,0x00,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xee,0x00,0x4e]
+
+# CHECK: vmullb.s16 q3, q4, q3 @ encoding: [0x19,0xee,0x06,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x19,0xee,0x06,0x6e]
+
+# CHECK: vmullb.s32 q3, q5, q6 @ encoding: [0x2b,0xee,0x0c,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2b,0xee,0x0c,0x6e]
+
+# CHECK: vmullt.s8 q0, q6, q2 @ encoding: [0x0d,0xee,0x04,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xee,0x04,0x1e]
+
+# CHECK: vmullt.s16 q0, q0, q2 @ encoding: [0x11,0xee,0x04,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x11,0xee,0x04,0x1e]
+
+# CHECK: vmullt.s32 q2, q4, q4 @ encoding: [0x29,0xee,0x08,0x5e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x29,0xee,0x08,0x5e]
+
+# CHECK: vmullb.p8 q2, q3, q7 @ encoding: [0x37,0xee,0x0e,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x0e,0x4e]
+
+# CHECK: vmullb.p16 q0, q1, q3 @ encoding: [0x33,0xfe,0x06,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x06,0x0e]
+
+# CHECK: vmullt.p8 q1, q1, q7 @ encoding: [0x33,0xee,0x0e,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x0e,0x3e]
+
+# CHECK: vmullt.p16 q0, q7, q7 @ encoding: [0x3f,0xfe,0x0e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x0e,0x1e]
+
+# CHECK: vmulh.s8 q0, q4, q5 @ encoding: [0x09,0xee,0x0b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x09,0xee,0x0b,0x0e]
+
+# CHECK: vmulh.s16 q0, q7, q4 @ encoding: [0x1f,0xee,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xee,0x09,0x0e]
+
+# CHECK: vmulh.s32 q0, q7, q4 @ encoding: [0x2f,0xee,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2f,0xee,0x09,0x0e]
+
+# CHECK: vmulh.u8 q3, q5, q2 @ encoding: [0x0b,0xfe,0x05,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0b,0xfe,0x05,0x6e]
+
+# CHECK: vmulh.u16 q2, q7, q4 @ encoding: [0x1f,0xfe,0x09,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xfe,0x09,0x4e]
+
+# CHECK: vmulh.u32 q1, q3, q2 @ encoding: [0x27,0xfe,0x05,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x27,0xfe,0x05,0x2e]
+
+# CHECK: vrmulh.s8 q1, q1, q2 @ encoding: [0x03,0xee,0x05,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x03,0xee,0x05,0x3e]
+
+# CHECK: vrmulh.s16 q1, q1, q2 @ encoding: [0x13,0xee,0x05,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x13,0xee,0x05,0x3e]
+
+# CHECK: vrmulh.s32 q3, q1, q0 @ encoding: [0x23,0xee,0x01,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xee,0x01,0x7e]
+
+# CHECK: vrmulh.u8 q1, q6, q0 @ encoding: [0x0d,0xfe,0x01,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xfe,0x01,0x3e]
+
+# CHECK: vrmulh.u16 q4, q3, q6 @ encoding: [0x17,0xfe,0x0d,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x17,0xfe,0x0d,0x9e]
+
+# CHECK: vrmulh.u32 q1, q2, q2 @ encoding: [0x25,0xfe,0x05,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x25,0xfe,0x05,0x3e]
+
+# CHECK: vqmovnb.s16 q0, q1 @ encoding: [0x33,0xee,0x03,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x03,0x0e]
+
+# CHECK: vqmovnt.s16 q2, q0 @ encoding: [0x33,0xee,0x01,0x5e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x01,0x5e]
+
+# CHECK: vqmovnb.s32 q0, q5 @ encoding: [0x37,0xee,0x0b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x0b,0x0e]
+
+# CHECK: vqmovnt.s32 q0, q1 @ encoding: [0x37,0xee,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x03,0x1e]
+
+# CHECK: vqmovnb.u16 q0, q4 @ encoding: [0x33,0xfe,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x09,0x0e]
+
+# CHECK: vqmovnt.u16 q0, q7 @ encoding: [0x33,0xfe,0x0f,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x0f,0x1e]
+
+# CHECK: vqmovnb.u32 q0, q4 @ encoding: [0x37,0xfe,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xfe,0x09,0x0e]
+
+# CHECK: vqmovnt.u32 q0, q2 @ encoding: [0x37,0xfe,0x05,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xfe,0x05,0x1e]
+
+# CHECK: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xee,0x09,0x2e]
+
+# CHECK: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xee,0x09,0x3e]
+
+# CHECK: vcvtb.f32.f16 q0, q3 @ encoding: [0x3f,0xfe,0x07,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x07,0x0e]
+
+# CHECK: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x03,0x1e]
+
+# CHECK: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xee,0x09,0x2e]
+
+# CHECK: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x03,0x1e]
+
+# CHECK: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb2,0xee,0xc0,0x0b]
+
+# CHECK: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf3,0xee,0xc2,0x0b]
+
+# CHECK: vqmovunb.s16 q0, q3 @ encoding: [0x31,0xee,0x87,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x87,0x0e]
+
+# CHECK: vqmovunt.s16 q4, q1 @ encoding: [0x31,0xee,0x83,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x83,0x9e]
+
+# CHECK: vqmovunb.s32 q1, q7 @ encoding: [0x35,0xee,0x8f,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x8f,0x2e]
+
+# CHECK: vqmovunt.s32 q0, q2 @ encoding: [0x35,0xee,0x85,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x85,0x1e]
+
+# CHECK: vmovnb.i16 q1, q5 @ encoding: [0x31,0xfe,0x8b,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x8b,0x2e]
+
+# CHECK: vmovnt.i16 q0, q0 @ encoding: [0x31,0xfe,0x81,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x81,0x1e]
+
+# CHECK: vmovnb.i32 q1, q0 @ encoding: [0x35,0xfe,0x81,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x81,0x2e]
+
+# CHECK: vmovnt.i32 q3, q3 @ encoding: [0x35,0xfe,0x87,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x87,0x7e]
+
+# CHECK: vhcadd.s8 q3, q7, q5, #90 @ encoding: [0x0e,0xee,0x0a,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0e,0xee,0x0a,0x6f]
+
+# CHECK: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xee,0x0c,0x0f]
+
+# CHECK: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xee,0x0c,0x0f]
+
+# CHECK: vhcadd.s16 q3, q1, q0, #270 @ encoding: [0x12,0xee,0x00,0x7f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xee,0x00,0x7f]
+
+# CHECK: vhcadd.s32 q3, q4, q5, #90 @ encoding: [0x28,0xee,0x0a,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xee,0x0a,0x6f]
+
+# CHECK: vhcadd.s32 q6, q7, q2, #270 @ encoding: [0x2e,0xee,0x04,0xdf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2e,0xee,0x04,0xdf]
+
+# CHECK: vadc.i32 q1, q0, q2 @ encoding: [0x30,0xee,0x04,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xee,0x04,0x2f]
+
+# CHECK: vadci.i32 q0, q1, q1 @ encoding: [0x32,0xee,0x02,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xee,0x02,0x1f]
+
+# CHECK: vcadd.i8 q1, q0, q2, #90 @ encoding: [0x00,0xfe,0x04,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xfe,0x04,0x2f]
+
+# CHECK: vcadd.i16 q0, q2, q3, #90 @ encoding: [0x14,0xfe,0x06,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xfe,0x06,0x0f]
+
+# CHECK: vcadd.i16 q0, q5, q5, #270 @ encoding: [0x1a,0xfe,0x0a,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xfe,0x0a,0x1f]
+
+# CHECK: vcadd.i32 q4, q2, q5, #90 @ encoding: [0x24,0xfe,0x0a,0x8f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xfe,0x0a,0x8f]
+
+# CHECK: vcadd.i32 q5, q5, q0, #270 @ encoding: [0x2a,0xfe,0x00,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xfe,0x00,0xbf]
+
+# CHECK: vsbc.i32 q3, q1, q1 @ encoding: [0x32,0xfe,0x02,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xfe,0x02,0x6f]
+
+# CHECK: vsbci.i32 q2, q6, q2 @ encoding: [0x3c,0xfe,0x04,0x5f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3c,0xfe,0x04,0x5f]
+
+# CHECK: vqdmullb.s16 q0, q4, q5 @ encoding: [0x38,0xee,0x0b,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x38,0xee,0x0b,0x0f]
+
+# CHECK: vqdmullt.s16 q0, q6, q5 @ encoding: [0x3c,0xee,0x0b,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3c,0xee,0x0b,0x1f]
+
+# CHECK: vqdmullb.s32 q0, q3, q7 @ encoding: [0x36,0xfe,0x0f,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x36,0xfe,0x0f,0x0f]
+
+# CHECK: vqdmullt.s32 q0, q7, q5 @ encoding: [0x3e,0xfe,0x0b,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3e,0xfe,0x0b,0x1f]
Propchange: llvm/trunk/test/MC/Disassembler/ARM/mve-qdest-qsrc.txt
------------------------------------------------------------------------------
svn:eol-style = native
Propchange: llvm/trunk/test/MC/Disassembler/ARM/mve-qdest-qsrc.txt
------------------------------------------------------------------------------
svn:keywords = Rev Date Author URL Id
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