[PATCH] D63628: AMD K10 (Barcelona) Initial Scheduler model

[Javed Absar via Phabricator via llvm-commits]

javed.absar added inline comments.


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Comment at: lib/Target/X86/X86ScheduleBarcelona.td:185
+                         list<int> Res, int UOps> {
+  defm : BnWriteRes<SchedRW, !listconcat([IntScheduler], ExePorts),
+                    Lat, !listconcat([1], Res), UOps>;
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You can use 'listA # listB'  to concatenate to improve readability 


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63628/new/

https://reviews.llvm.org/D63628