[PATCH] D63635: [COFF, ARM64] Fix encoding of debugtrap for Windows

[Tom Tan via Phabricator via llvm-commits]

TomTan created this revision.
TomTan added reviewers: efriedma, rnk.
Herald added subscribers: llvm-commits, kristof.beyls, javed.absar.
Herald added a project: LLVM.

On Windows ARM64, intrinsic `__debugbreak` is compiled into `brk #0xF000` which is mapped to `llvm.debugtrap` in Clang. Instruction `brk #F000` is the defined break point instruction on ARM64 which is recognized by Windows debugger and exception handling code, so `llvm.debugtrap` should map to it instead of redirecting to `llvm.trap` (brk #1) as the default implementation.


Repository:
  rL LLVM

https://reviews.llvm.org/D63635

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64InstrInfo.td
  test/CodeGen/AArch64/trap.ll


Index: test/CodeGen/AArch64/trap.ll
===================================================================
--- test/CodeGen/AArch64/trap.ll
+++ test/CodeGen/AArch64/trap.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=aarch64-windows | FileCheck %s
+
+; CHECK-LABEL: test1:
+; CHECK: brk #0xf000
+define i32 @test1() noreturn nounwind  {
+entry:
+  tail call void @llvm.debugtrap( )
+  unreachable
+}
+
+declare void @llvm.debugtrap() nounwind 
+
Index: lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- lib/Target/AArch64/AArch64InstrInfo.td
+++ lib/Target/AArch64/AArch64InstrInfo.td
@@ -135,6 +135,7 @@
                        AssemblerPredicate<"FeatureMTE", "mte">;
 def IsLE             : Predicate<"Subtarget->isLittleEndian()">;
 def IsBE             : Predicate<"!Subtarget->isLittleEndian()">;
+def IsWindows        : Predicate<"Subtarget->isTargetWindows()">;
 def UseAlternateSExtLoadCVTF32
     : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">;
 
@@ -6116,6 +6117,7 @@
 
 // __builtin_trap() uses the BRK instruction on AArch64.
 def : Pat<(trap), (BRK 1)>;
+def : Pat<(debugtrap), (BRK 0xF000)>, Requires<[IsWindows]>;
 
 // Multiply high patterns which multiply the lower subvector using smull/umull
 // and the upper subvector with smull2/umull2. Then shuffle the high the high
Index: lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelLowering.cpp
+++ lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -551,6 +551,8 @@
 
   // Trap.
   setOperationAction(ISD::TRAP, MVT::Other, Legal);
+  if (Subtarget->isTargetWindows())
+    setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
 
   // We combine OR nodes for bitfield operations.
   setTargetDAGCombine(ISD::OR);


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