[llvm] r363856 - [TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG support

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Wed Jun 19 11:34:58 2019
New Revision: 363856

URL: http://llvm.org/viewvc/llvm-project?rev=363856&view=rev
Log:
[TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG support

Move 'lowest' demanded elt -> bitcast fold out of ZERO_EXTEND_VECTOR_INREG into ANY_EXTEND_VECTOR_INREG case.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=363856&r1=363855&r2=363856&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun 19 11:34:58 2019
@@ -1381,19 +1381,11 @@ bool TargetLowering::SimplifyDemandedBit
     bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
 
     // If none of the top bits are demanded, convert this into an any_extend.
-    if (DemandedBits.getActiveBits() <= InBits) {
-      // If we only need the non-extended bits of the bottom element
-      // then we can just bitcast to the result.
-      if (IsVecInReg && DemandedElts == 1 &&
-          VT.getSizeInBits() == SrcVT.getSizeInBits() &&
-          TLO.DAG.getDataLayout().isLittleEndian())
-        return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
-
+    if (DemandedBits.getActiveBits() <= InBits)
       return TLO.CombineTo(
           Op, TLO.DAG.getNode(IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG
                                          : ISD::ANY_EXTEND,
                               dl, VT, Src));
-    }
 
     APInt InDemandedBits = DemandedBits.trunc(InBits);
     APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
@@ -1444,12 +1436,21 @@ bool TargetLowering::SimplifyDemandedBit
                               dl, VT, Src));
     break;
   }
-  case ISD::ANY_EXTEND: {
-    // TODO: Add ISD::ANY_EXTEND_VECTOR_INREG support.
+  case ISD::ANY_EXTEND:
+  case ISD::ANY_EXTEND_VECTOR_INREG: {
     SDValue Src = Op.getOperand(0);
     EVT SrcVT = Src.getValueType();
     unsigned InBits = SrcVT.getScalarSizeInBits();
     unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
+    bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG;
+
+    // If we only need the bottom element then we can just bitcast.
+    // TODO: Handle ANY_EXTEND?
+    if (IsVecInReg && DemandedElts == 1 &&
+        VT.getSizeInBits() == SrcVT.getSizeInBits() &&
+        TLO.DAG.getDataLayout().isLittleEndian())
+      return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
+
     APInt InDemandedBits = DemandedBits.trunc(InBits);
     APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
     if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,