[PATCH] D63494: [AMDGPU] Fix for branch offset hardware workaround
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 19 11:22:01 PDT 2019
rampitec added inline comments.
================
Comment at: lib/Target/AMDGPU/SOPInstructions.td:972
+multiclass SOPP_Real <bits<7> op, dag ins, string asm, list<dag> pattern = []> {
+ def "" : SOPP<op, ins, asm, pattern>;
----------------
SOPP_With_Relaxation maybe?
================
Comment at: lib/Target/AMDGPU/SOPInstructions.td:974
+ def "" : SOPP<op, ins, asm, pattern>;
+ def _PAD_S_NOP : SOPP64<op, ins, asm, pattern>;
+}
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Can yo use InstrMapping mapping here to avoid switches?
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D63494/new/
https://reviews.llvm.org/D63494
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