[PATCH] D63411: [RISCV] Specify registers used in DWARF exception handling

Edward Jones via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 19 04:23:05 PDT 2019


edward-jones updated this revision to Diff 205544.
edward-jones retitled this revision from "[WIP][RISCV] Specify registers used in DWARF exception handling" to "[RISCV] Specify registers used in DWARF exception handling".
edward-jones edited the summary of this revision.
edward-jones added a comment.

Rebased against master


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63411/new/

https://reviews.llvm.org/D63411

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h


Index: lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.h
+++ lib/Target/RISCV/RISCVISelLowering.h
@@ -128,6 +128,16 @@
   bool isDesirableToCommuteWithShift(const SDNode *N,
                                      CombineLevel Level) const override;
 
+  /// If a physical register, this returns the register that receives the
+  /// exception address on entry to an EH pad.
+  unsigned
+  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
+
+  /// If a physical register, this returns the register that receives the
+  /// exception typeid on entry to a landing pad.
+  unsigned
+  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
+
 private:
   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
                         const SmallVectorImpl<ISD::InputArg> &Ins,
Index: lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.cpp
+++ lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2522,3 +2522,13 @@
     Result = Builder.CreateTrunc(Result, Builder.getInt32Ty());
   return Result;
 }
+
+unsigned RISCVTargetLowering::getExceptionPointerRegister(
+    const Constant *PersonalityFn) const {
+  return RISCV::X10;
+}
+
+unsigned RISCVTargetLowering::getExceptionSelectorRegister(
+    const Constant *PersonalityFn) const {
+  return RISCV::X11;
+}


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