[PATCH] D62592: [RISCV] Add assembler support for RVC HINT instructions

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 added inline comments.


================
Comment at: lib/Target/RISCV/RISCVInstrInfoC.td:577
+  let Inst{6-2} = imm{4-0};
+  let isAsmParserOnly = 1;
+}
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luismarques wrote:
> shiva0217 wrote:
> > We could remove "let isAsmParserOnly = 1" and add "let Inst{11} = 0". So tablegen won't complain the encoding ambiguous and will invoke DecodeGPRX0RegisterClass in RISCVGenDisassemblerTables.inc.
> If I do that then the (non-hint) `c.li` instruction instruction is decoded as `<unknown>`.
> To correctly decode both the regular and the hint instructions wouldn't we need to add support for decoding based on the operand classes?
Oh, I think you're right.
We could define "let Inst{11-7} = 0;" and the decoder method "let DecoderMethod = "DecodeC_LI_HINT";"
So only C_LI_HINT will match the decoder "DecodeC_LI_HINT" and using the decoder to add X0 register.
Something like
  static DecodeStatus DecodeC_LI_HINT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {
    DecodeStatus S = MCDisassembler::Success;
  
    unsigned Rd = fieldFromInstruction(Insn, 7, 5);
    uint64_t Simm6 = fieldFromInstruction(Insn, 2, 5) |
                     fieldFromInstruction(Insn, 12, 1) << 5;
  
    DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
  
    if (decodeSImmOperand<6>(Inst, Simm6, Address, Decoder) ==
        MCDisassembler::Fail) {
      return MCDisassembler::Fail;
    }
  
    return S;
  }
And some of the decoder methods might be shared if the hint instructions have the same format.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D62592/new/

https://reviews.llvm.org/D62592