[PATCH] D63494: [AMDGPU] Fix for branch offset hardware workaround

Tue Jun 18 08:41:31 PDT 2019

rtaylor marked an inline comment as done.
rtaylor added inline comments.

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Comment at: lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp:56-57

+static unsigned getRelaxedOpcode(const MCInst &Inst) {
+  unsigned Op = Inst.getOpcode();
+  switch (Op) {
----------------
rtaylor wrote:
> arsenm wrote:
> > I would much rather avoid the proliferation of junk opcodes for this. Can you use a bundle or another way to add an independent nop instruction?
> I'm not sure that's possible, relaxInstruction is return the MCInst Res but I can't say for sure as I've never worked with bundles and I'm not sure how the compiler treats them. I agree though that this would be more ideal than having new 64 bit instructions.
This would require a bundle to have a specific opcode, which from what I can see they do not.

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63494/new/

https://reviews.llvm.org/D63494