[PATCH] D63494: [AMDGPU] Fix for branch offset hardware workaround

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp:56-57
 
+static unsigned getRelaxedOpcode(const MCInst &Inst) {
+  unsigned Op = Inst.getOpcode();
+  switch (Op) {
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I would much rather avoid the proliferation of junk opcodes for this. Can you use a bundle or another way to add an independent nop instruction?


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Comment at: test/MC/AMDGPU/offsetbug.s:18-20
+	tbuffer_load_format_x v0, v4, s[8:11],  format:22, 0 idxen offset:4
+	tbuffer_load_format_xyzw v[9:12], v4, s[8:11],  format:56, 0 idxen offset:8
+	tbuffer_load_format_xyzw v[13:16], v4, s[8:11],  format:56, 0 idxen offset:12
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Can you use trivial instructions for sizes? I don't trust the size of most instructions to stay the same


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Comment at: test/MC/AMDGPU/offsetbug.s:82-83
+	s_nop 0
+        s_nop 0
+	s_nop 0
+	s_nop 0
----------------
Formatting


Repository:
  rL LLVM

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  https://reviews.llvm.org/D63494/new/

https://reviews.llvm.org/D63494