[llvm] r363330 - [X86Disassembler] Unify the EVEX and VEX code in emitContextTable. Merge the ATTR_VEXL/ATTR_EVEXL bits. NFCI
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 13 15:15:25 PDT 2019
Author: ctopper
Date: Thu Jun 13 15:15:25 2019
New Revision: 363330
URL: http://llvm.org/viewvc/llvm-project?rev=363330&view=rev
Log:
[X86Disassembler] Unify the EVEX and VEX code in emitContextTable. Merge the ATTR_VEXL/ATTR_EVEXL bits. NFCI
Merging the two bits shrinks the context table from 16384 bytes to 8192 bytes.
Remove the ATTRIBUTE_BITS macro and just create an enum directly. Then fix the ATTR_max define to be 8192 to reflect the table size so we stop hardcoding it separately.
Modified:
llvm/trunk/include/llvm/Support/X86DisassemblerDecoderCommon.h
llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
Modified: llvm/trunk/include/llvm/Support/X86DisassemblerDecoderCommon.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/X86DisassemblerDecoderCommon.h?rev=363330&r1=363329&r2=363330&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/X86DisassemblerDecoderCommon.h (original)
+++ llvm/trunk/include/llvm/Support/X86DisassemblerDecoderCommon.h Thu Jun 13 15:15:25 2019
@@ -46,29 +46,23 @@ namespace X86Disassembler {
// Attributes of an instruction that must be known before the opcode can be
// processed correctly. Most of these indicate the presence of particular
// prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
-#define ATTRIBUTE_BITS \
- ENUM_ENTRY(ATTR_NONE, 0x00) \
- ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \
- ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \
- ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \
- ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \
- ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \
- ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \
- ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \
- ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \
- ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \
- ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \
- ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \
- ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \
- ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \
- ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13))
-
-#define ENUM_ENTRY(n, v) n = v,
enum attributeBits {
- ATTRIBUTE_BITS
- ATTR_max
+ ATTR_NONE = 0x00,
+ ATTR_64BIT = 0x1 << 0,
+ ATTR_XS = 0x1 << 1,
+ ATTR_XD = 0x1 << 2,
+ ATTR_REXW = 0x1 << 3,
+ ATTR_OPSIZE = 0x1 << 4,
+ ATTR_ADSIZE = 0x1 << 5,
+ ATTR_VEX = 0x1 << 6,
+ ATTR_VEXL = 0x1 << 7,
+ ATTR_EVEX = 0x1 << 8,
+ ATTR_EVEXL2 = 0x1 << 9,
+ ATTR_EVEXK = 0x1 << 10,
+ ATTR_EVEXKZ = 0x1 << 11,
+ ATTR_EVEXB = 0x1 << 12,
+ ATTR_max = 0x1 << 13,
};
-#undef ENUM_ENTRY
// Combinations of the above attributes that are relevant to instruction
// decode. Although other combinations are possible, they can be reduced to
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp?rev=363330&r1=363329&r2=363330&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp Thu Jun 13 15:15:25 2019
@@ -882,7 +882,7 @@ static int getID(struct InternalInstruct
if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]))
attrMask |= ATTR_EVEXK;
if (lFromEVEX4of4(insn->vectorExtensionPrefix[3]))
- attrMask |= ATTR_EVEXL;
+ attrMask |= ATTR_VEXL;
if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]))
attrMask |= ATTR_EVEXL2;
} else if (insn->vectorExtensionType == TYPE_VEX_3B) {
Modified: llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp?rev=363330&r1=363329&r2=363330&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp (original)
+++ llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp Thu Jun 13 15:15:25 2019
@@ -888,67 +888,44 @@ void DisassemblerTables::emitInstruction
}
void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
- const unsigned int tableSize = 16384;
o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
- "[" << tableSize << "] = {\n";
+ "[" << ATTR_max << "] = {\n";
i++;
- for (unsigned index = 0; index < tableSize; ++index) {
+ for (unsigned index = 0; index < ATTR_max; ++index) {
o.indent(i * 2);
- if (index & ATTR_EVEX) {
- o << "IC_EVEX";
- if (index & ATTR_EVEXL2)
+ if ((index & ATTR_EVEX) || (index & ATTR_VEX) || (index & ATTR_VEXL)) {
+ if (index & ATTR_EVEX)
+ o << "IC_EVEX";
+ else
+ o << "IC_VEX";
+
+ if ((index & ATTR_EVEX) && (index & ATTR_EVEXL2))
o << "_L2";
- else if (index & ATTR_EVEXL)
+ else if (index & ATTR_VEXL)
o << "_L";
+
if (index & ATTR_REXW)
o << "_W";
+
if (index & ATTR_OPSIZE)
o << "_OPSIZE";
else if (index & ATTR_XD)
o << "_XD";
else if (index & ATTR_XS)
o << "_XS";
- if (index & ATTR_EVEXKZ)
- o << "_KZ";
- else if (index & ATTR_EVEXK)
- o << "_K";
- if (index & ATTR_EVEXB)
- o << "_B";
+
+ if ((index & ATTR_EVEX)) {
+ if (index & ATTR_EVEXKZ)
+ o << "_KZ";
+ else if (index & ATTR_EVEXK)
+ o << "_K";
+
+ if (index & ATTR_EVEXB)
+ o << "_B";
+ }
}
- else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
- o << "IC_VEX_L_W_OPSIZE";
- else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
- o << "IC_VEX_L_W_XD";
- else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
- o << "IC_VEX_L_W_XS";
- else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
- o << "IC_VEX_L_W";
- else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
- o << "IC_VEX_L_OPSIZE";
- else if ((index & ATTR_VEXL) && (index & ATTR_XD))
- o << "IC_VEX_L_XD";
- else if ((index & ATTR_VEXL) && (index & ATTR_XS))
- o << "IC_VEX_L_XS";
- else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
- o << "IC_VEX_W_OPSIZE";
- else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
- o << "IC_VEX_W_XD";
- else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
- o << "IC_VEX_W_XS";
- else if (index & ATTR_VEXL)
- o << "IC_VEX_L";
- else if ((index & ATTR_VEX) && (index & ATTR_REXW))
- o << "IC_VEX_W";
- else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
- o << "IC_VEX_OPSIZE";
- else if ((index & ATTR_VEX) && (index & ATTR_XD))
- o << "IC_VEX_XD";
- else if ((index & ATTR_VEX) && (index & ATTR_XS))
- o << "IC_VEX_XS";
- else if (index & ATTR_VEX)
- o << "IC_VEX";
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
o << "IC_64BIT_REXW_XS";
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
@@ -1003,12 +980,7 @@ void DisassemblerTables::emitContextTabl
else
o << "IC";
- if (index < tableSize - 1)
- o << ",";
- else
- o << " ";
-
- o << " /* " << index << " */";
+ o << ", /* " << index << " */";
o << "\n";
}
More information about the llvm-commits
mailing list