[PATCH] D63281: [TargetLowering] Add SimplifyMultipleUseDemandedBits

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, arsenm, efriedma, spatel, lebedev.ri, nikic.
Herald added subscribers: tpr, javed.absar, nhaehnle, wdng, jvesely.
Herald added a project: LLVM.

This patch introduces the DAG version of SimplifyMultipleUseDemandedBits, which attempts to peek through ops (mainly and/or/xor so far) that don't contribute to the demandedbits/elts of a node - which means we can do this even in cases where we have multiple uses of an op, which normally requires us to demanded all bits/elts. The intention is to remove a similar instruction - SelectionDAG::GetDemandedBits - once SimplifyMultipleUseDemandedBits has matured.

The InstCombine version of SimplifyMultipleUseDemandedBits can constant fold which I haven't added here yet, and so far I've only wired this up to some basic binops (and/or/xor/add/sub/mul) to demonstrate its use.

We do see a couple of regressions that need to be addressed:

- AMDGPU unsigned dot product codegen retains an AND mask that it previously removed (but otherwise the dotproduct codegen is a lot better)
- X86/AVX2 has poor handling of vector ANY_EXTEND/ANY_EXTEND_VECTOR_INREG - it prematurely gets converted to ZERO_EXTEND_VECTOR_INREG

Both these cases look like they can be fixed up afterwards but I'd like to get code owner's feedback first.


Repository:
  rL LLVM

https://reviews.llvm.org/D63281

Files:
  include/llvm/CodeGen/TargetLowering.h
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  test/CodeGen/AArch64/bitfield-insert.ll
  test/CodeGen/AMDGPU/idot4s.ll
  test/CodeGen/AMDGPU/idot4u.ll
  test/CodeGen/AMDGPU/idot8s.ll
  test/CodeGen/AMDGPU/idot8u.ll
  test/CodeGen/AMDGPU/sdiv.ll
  test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
  test/CodeGen/X86/2012-08-07-CmpISelBug.ll
  test/CodeGen/X86/vector-fshl-128.ll
  test/CodeGen/X86/vector-reduce-mul-widen.ll
  test/CodeGen/X86/vector-reduce-mul.ll

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