[PATCH] D63246: [X86][SSE] Prevent misaligned non-temporal vector load/store combines

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, andreadb, wristow, lebedev.ri.
Herald added a project: LLVM.

For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway.

First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets.


Repository:
  rL LLVM

https://reviews.llvm.org/D63246

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/merge-consecutive-stores-nt.ll

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