[llvm] r363190 - [AMDGPU] more gfx1010 tests. NFC.
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 12 11:44:11 PDT 2019
Author: rampitec
Date: Wed Jun 12 11:44:11 2019
New Revision: 363190
URL: http://llvm.org/viewvc/llvm-project?rev=363190&view=rev
Log:
[AMDGPU] more gfx1010 tests. NFC.
Added:
llvm/trunk/test/MC/AMDGPU/vop3-literal.s
Modified:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
llvm/trunk/test/CodeGen/AMDGPU/basic-branch.ll
llvm/trunk/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
llvm/trunk/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
llvm/trunk/test/CodeGen/AMDGPU/smem-war-hazard.mir
llvm/trunk/test/CodeGen/AMDGPU/v_cndmask.ll
llvm/trunk/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
llvm/trunk/test/MC/AMDGPU/expressions-gfx10.s
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir?rev=363190&r1=363189&r2=363190&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir Wed Jun 12 11:44:11 2019
@@ -12,7 +12,7 @@ regBankSelected: true
# GCN: global_addrspace
# GCN: [[PTR:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
-# GCN: FLAT_LOAD_DWORD [[PTR]], 0, 0, 0
+# GCN: FLAT_LOAD_DWORD [[PTR]], 0, 0, 0, 0
body: |
bb.0:
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir?rev=363190&r1=363189&r2=363190&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir Wed Jun 12 11:44:11 2019
@@ -15,12 +15,12 @@ regBankSelected: true
# GCN: [[PTR:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
# Immediate offset:
-# SICI: S_LOAD_DWORD_IMM [[PTR]], 1, 0
-# VI: S_LOAD_DWORD_IMM [[PTR]], 4, 0
+# SICI: S_LOAD_DWORD_IMM [[PTR]], 1, 0, 0
+# VI: S_LOAD_DWORD_IMM [[PTR]], 4, 0, 0
# Max immediate offset for SI
-# SICI: S_LOAD_DWORD_IMM [[PTR]], 255, 0
-# VI: S_LOAD_DWORD_IMM [[PTR]], 1020, 0
+# SICI: S_LOAD_DWORD_IMM [[PTR]], 255, 0, 0
+# VI: S_LOAD_DWORD_IMM [[PTR]], 1020, 0, 0
# Immediate overflow for SI
# SI: [[K1024:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1024
@@ -50,8 +50,8 @@ regBankSelected: true
# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
-# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
-# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 4294967295, 0
+# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0, 0
+# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 4294967295, 0, 0
# Immediate overflow for CI
# GCN: [[K_LO:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
@@ -64,7 +64,7 @@ regBankSelected: true
# GCN-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
# GCN: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
# GCN: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
-# GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
+# GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0, 0
# Max 32-bit byte offset
# SIVI: [[K4294967292:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4294967292
@@ -82,8 +82,8 @@ regBankSelected: true
# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
-# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
-# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741824, 0
+# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0, 0
+# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741824, 0, 0
# Pointer loads
# GCN: [[AS0:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0
Modified: llvm/trunk/test/CodeGen/AMDGPU/basic-branch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/basic-branch.ll?rev=363190&r1=363189&r2=363190&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/basic-branch.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/basic-branch.ll Wed Jun 12 11:44:11 2019
@@ -1,5 +1,6 @@
; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
+; RUN: llc -O0 -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global,-WavefrontSize32,+WavefrontSize64 -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s
Modified: llvm/trunk/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll?rev=363190&r1=363189&r2=363190&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll Wed Jun 12 11:44:11 2019
@@ -1,7 +1,8 @@
; XUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,VI-DENORM %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,VI-FLUSH %s
-
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,SIVI,VI-DENORM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,SIVI,VI-FLUSH %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10,GFX8_10,GFX10-DENORM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10,GFX8_10,GFX10-FLUSH %s
; Make sure (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c)) doesn't
; make add an instruction if the fadd has more than one use.
@@ -16,13 +17,14 @@ declare float @llvm.fabs.f32(float) #1
; SI: v_mad_f32 [[A20:v[0-9]+]], -[[A18]], [[A17]], 1.0
; SI: buffer_store_dword [[A20]]
-; VI: v_add_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -1.0
-; VI: v_add_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -1.0
-; VI: v_cmp_gt_f32_e64 vcc, |v{{[0-9]+}}|, |v{{[0-9]+}}|
-; VI: v_cndmask_b32_e32
-; VI: v_add_f32_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, |v{{[0-9]+}}|
-; VI: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
-; VI: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, 1.0
+; GFX8_10: v_add_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -1.0
+; GFX8_10: v_add_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -1.0
+; GFX8_10: v_cmp_gt_f32_e64 {{vcc|vcc_lo}}, |v{{[0-9]+}}|, |v{{[0-9]+}}|
+; GFX8_10: v_cndmask_b32_e32
+; GFX8_10: v_add_f32_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, |v{{[0-9]+}}|
+; GFX8_10: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; VI: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, 1.0
+; GFX10: v_fma_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, 1.0
define amdgpu_kernel void @multiple_fadd_use_test_f32(float addrspace(1)* %out, float %x, float %y, float %z) #0 {
%a11 = fadd float %y, -1.0
%a12 = call float @llvm.fabs.f32(float %a11)
@@ -39,11 +41,12 @@ define amdgpu_kernel void @multiple_fadd
}
; GCN-LABEL: {{^}}multiple_use_fadd_fmac_f32:
-; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
-; GCN-DAG: v_mac_f32_e64 [[MAD:v[0-9]+]], [[X]], 2.0
-; GCN-DAG: buffer_store_dword [[MUL2]]
-; GCN-DAG: buffer_store_dword [[MAD]]
-; GCN: s_endpgm
+; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
+; SIVI-DAG: v_mac_f32_e64 [[MAD:v[0-9]+]], [[X]], 2.0
+; GFX10-DAG: v_fma_f32 [[MAD:v[0-9]+]], [[X]], 2.0, s{{[0-9]+}}
+; GCN-DAG: buffer_store_dword [[MUL2]]
+; GCN-DAG: buffer_store_dword [[MAD]]
+; GCN: s_endpgm
define amdgpu_kernel void @multiple_use_fadd_fmac_f32(float addrspace(1)* %out, float %x, [8 x i32], float %y) #0 {
%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
%mul2 = fmul fast float %x, 2.0
@@ -54,11 +57,12 @@ define amdgpu_kernel void @multiple_use_
}
; GCN-LABEL: {{^}}multiple_use_fadd_fmad_f32:
-; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |s{{[0-9]+}}|
-; GCN-DAG: v_mad_f32 [[MAD:v[0-9]+]], |[[X]]|, 2.0, v{{[0-9]+}}
-; GCN-DAG: buffer_store_dword [[MUL2]]
-; GCN-DAG: buffer_store_dword [[MAD]]
-; GCN: s_endpgm
+; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |s{{[0-9]+}}|
+; SIVI-DAG: v_mad_f32 [[MAD:v[0-9]+]], |[[X]]|, 2.0, v{{[0-9]+}}
+; GFX10-DAG: v_fma_f32 [[MAD:v[0-9]+]], 2.0, |[[X]]|, v{{[0-9]+}}
+; GCN-DAG: buffer_store_dword [[MUL2]]
+; GCN-DAG: buffer_store_dword [[MAD]]
+; GCN: s_endpgm
define amdgpu_kernel void @multiple_use_fadd_fmad_f32(float addrspace(1)* %out, float %x, float %y) #0 {
%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
%x.abs = call float @llvm.fabs.f32(float %x)
@@ -70,8 +74,10 @@ define amdgpu_kernel void @multiple_use_
}
; GCN-LABEL: {{^}}multiple_use_fadd_multi_fmad_f32:
-; GCN: v_mad_f32 {{v[0-9]+}}, |[[X:s[0-9]+]]|, 2.0, v{{[0-9]+}}
-; GCN: v_mad_f32 {{v[0-9]+}}, |[[X]]|, 2.0, v{{[0-9]+}}
+; SIVI: v_mad_f32 {{v[0-9]+}}, |[[X:s[0-9]+]]|, 2.0, v{{[0-9]+}}
+; SIVI: v_mad_f32 {{v[0-9]+}}, |[[X]]|, 2.0, v{{[0-9]+}}
+; GFX10: v_fma_f32 {{v[0-9]+}}, |[[X:s[0-9]+]]|, 2.0, {{s[0-9]+}}
+; GFX10: v_fma_f32 {{v[0-9]+}}, |[[X]]|, 2.0, {{s[0-9]+}}
define amdgpu_kernel void @multiple_use_fadd_multi_fmad_f32(float addrspace(1)* %out, float %x, float %y, float %z) #0 {
%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
%x.abs = call float @llvm.fabs.f32(float %x)
@@ -97,10 +103,11 @@ define amdgpu_kernel void @fmul_x2_xn2_f
}
; GCN-LABEL: {{^}}fmul_x2_xn3_f32:
-; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0xc0c00000
-; GCN: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[X:s[0-9]+]], [[K]]
-; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[X]], [[TMP0]]
-; GCN: buffer_store_dword [[RESULT]]
+; SIVI: v_mov_b32_e32 [[K:v[0-9]+]], 0xc0c00000
+; SIVI: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[X:s[0-9]+]], [[K]]
+; GFX10: v_mul_f32_e64 [[TMP0:v[0-9]+]], 0xc0c00000, [[X:s[0-9]+]]
+; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[X]], [[TMP0]]
+; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @fmul_x2_xn3_f32(float addrspace(1)* %out, float %x, float %y) #0 {
%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
%mul2 = fmul fast float %x, 2.0
@@ -111,14 +118,16 @@ define amdgpu_kernel void @fmul_x2_xn3_f
}
; GCN-LABEL: {{^}}multiple_fadd_use_test_f16:
-; VI: v_add_f16_e64 v{{[0-9]+}}, s{{[0-9]+}}, -1.0
-; VI: v_add_f16_e64 v{{[0-9]+}}, s{{[0-9]+}}, -1.0
-; VI: v_cmp_gt_f16_e64 vcc, |v{{[0-9]+}}|, |v{{[0-9]+}}|
-; VI: v_cndmask_b32_e32
-; VI: v_add_f16_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, |v{{[0-9]+}}|
-; VI: v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
-; VI-FLUSH: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, 1.0
-; VI-DENORM: v_fma_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, 1.0
+; GFX8_10: v_add_f16_e64 v{{[0-9]+}}, s{{[0-9]+}}, -1.0
+; GFX8_10: v_add_f16_e64 v{{[0-9]+}}, s{{[0-9]+}}, -1.0
+; GFX8_10: v_cmp_gt_f16_e64 {{vcc|vcc_lo}}, |v{{[0-9]+}}|, |v{{[0-9]+}}|
+; GFX8_10: v_cndmask_b32_e32
+; GFX8_10: v_add_f16_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, |v{{[0-9]+}}|
+; GFX8_10: v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; VI-FLUSH: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, 1.0
+; VI-DENORM: v_fma_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, 1.0
+; GFX10-DENORM: v_fmac_f16_e64 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}
+; GFX10-FLUSH: v_sub_f16_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}
define amdgpu_kernel void @multiple_fadd_use_test_f16(half addrspace(1)* %out, i16 zeroext %x.arg, i16 zeroext %y.arg, i16 zeroext %z.arg) #0 {
%x = bitcast i16 %x.arg to half
%y = bitcast i16 %y.arg to half
@@ -140,8 +149,10 @@ define amdgpu_kernel void @multiple_fadd
; GCN-LABEL: {{^}}multiple_use_fadd_fmac_f16:
; GCN-DAG: v_add_f16_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
-; VI-FLUSH-DAG: v_mac_f16_e64 [[MAD:v[0-9]+]], [[X]], 2.0
-; VI-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], [[X]], 2.0, v{{[0-9]+}}
+; VI-FLUSH-DAG: v_mac_f16_e64 [[MAD:v[0-9]+]], [[X]], 2.0
+; VI-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], [[X]], 2.0, v{{[0-9]+}}
+; GFX10-FLUSH-DAG: v_add_f16_e32 [[MAD:v[0-9]+]], s{{[0-9]+}}, [[MUL2]]
+; GFX10-DENORM-DAG: v_fmac_f16_e64 [[MAD:v[0-9]+]], [[X]], 2.0
; GCN-DAG: buffer_store_short [[MUL2]]
; GCN-DAG: buffer_store_short [[MAD]]
@@ -160,8 +171,10 @@ define amdgpu_kernel void @multiple_use_
; GCN-LABEL: {{^}}multiple_use_fadd_fmad_f16:
; GCN-DAG: v_add_f16_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |s{{[0-9]+}}|
-; VI-FLUSH-DAG: v_mad_f16 [[MAD:v[0-9]+]], |[[X]]|, 2.0, v{{[0-9]+}}
-; VI-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], |[[X]]|, 2.0, v{{[0-9]+}}
+; VI-FLUSH-DAG: v_mad_f16 [[MAD:v[0-9]+]], |[[X]]|, 2.0, v{{[0-9]+}}
+; VI-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], |[[X]]|, 2.0, v{{[0-9]+}}
+; GFX10-FLUSH-DAG: v_add_f16_e32 [[MAD:v[0-9]+]], s{{[0-9]+}}, [[MUL2]]
+; GFX10-DENORM-DAG: v_fmac_f16_e64 [[MAD:v[0-9]+]], |[[X]]|, 2.0
; GCN-DAG: buffer_store_short [[MUL2]]
; GCN-DAG: buffer_store_short [[MAD]]
@@ -185,6 +198,12 @@ define amdgpu_kernel void @multiple_use_
; VI-DENORM: v_fma_f16 {{v[0-9]+}}, |[[X:s[0-9]+]]|, 2.0, v{{[0-9]+}}
; VI-DENORM: v_fma_f16 {{v[0-9]+}}, |[[X]]|, 2.0, v{{[0-9]+}}
+; GFX10-FLUSH: v_add_f16_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |{{s[0-9]+}}|
+; GFX10-FLUSH: v_add_f16_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[MUL2]]
+; GFX10-FLUSH: v_add_f16_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[MUL2]]
+; GFX10-DENORM: v_fmac_f16_e64 {{v[0-9]+}}, |[[X:s[0-9]+]]|, 2.0
+; GFX10-DENORM: v_fmac_f16_e64 {{v[0-9]+}}, |[[X]]|, 2.0
+
define amdgpu_kernel void @multiple_use_fadd_multi_fmad_f16(half addrspace(1)* %out, i16 zeroext %x.arg, i16 zeroext %y.arg, i16 zeroext %z.arg) #0 {
%x = bitcast i16 %x.arg to half
%y = bitcast i16 %y.arg to half
@@ -215,10 +234,11 @@ define amdgpu_kernel void @fmul_x2_xn2_f
}
; GCN-LABEL: {{^}}fmul_x2_xn3_f16:
-; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0xc600
-; GCN: v_mul_f16_e32 [[TMP0:v[0-9]+]], [[X:s[0-9]+]], [[K]]
-; GCN: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[X]], [[TMP0]]
-; GCN: buffer_store_short [[RESULT]]
+; SIVI: v_mov_b32_e32 [[K:v[0-9]+]], 0xc600
+; SIVI: v_mul_f16_e32 [[TMP0:v[0-9]+]], [[X:s[0-9]+]], [[K]]
+; GFX10: v_mul_f16_e64 [[TMP0:v[0-9]+]], 0xc600, [[X:s[0-9]+]]
+; GCN: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[X]], [[TMP0]]
+; GCN: buffer_store_short [[RESULT]]
define amdgpu_kernel void @fmul_x2_xn3_f16(half addrspace(1)* %out, i16 zeroext %x.arg, i16 zeroext %y.arg) #0 {
%x = bitcast i16 %x.arg to half
%y = bitcast i16 %y.arg to half
Modified: llvm/trunk/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir?rev=363190&r1=363189&r2=363190&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir Wed Jun 12 11:44:11 2019
@@ -1,6 +1,6 @@
# RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK,GCX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK,GFX9 %s
-# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK,GFX10 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK,GFX10 %s
# GCN-LABEL: name: break_smem_clause_simple_load_smrd8_ptr_hidden_bundle
# GCN: }
Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll?rev=363190&r1=363189&r2=363190&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll Wed Jun 12 11:44:11 2019
@@ -1,9 +1,10 @@
-; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
-
-; SI-LABEL: {{^}}gs_const:
-; SI-NOT: v_cmpx
-; SI: s_mov_b64 exec, 0
+; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
+; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s
+
+; GCN-LABEL: {{^}}gs_const:
+; GCN-NOT: v_cmpx
+; GCN: s_mov_b64 exec, 0
define amdgpu_gs void @gs_const() {
%tmp = icmp ule i32 0, 3
%tmp1 = select i1 %tmp, float 1.000000e+00, float -1.000000e+00
@@ -16,11 +17,12 @@ define amdgpu_gs void @gs_const() {
ret void
}
-; SI-LABEL: {{^}}vcc_implicit_def:
-; SI-NOT: v_cmp_gt_f32_e32 vcc,
-; SI: v_cmp_gt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0, v{{[0-9]+}}
+; GCN-LABEL: {{^}}vcc_implicit_def:
+; GCN-NOT: v_cmp_gt_f32_e32 vcc,
+; GCN: v_cmp_gt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0, v{{[0-9]+}}
; SI: v_cmpx_le_f32_e32 vcc, 0, v{{[0-9]+}}
-; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]]
+; GFX10: v_cmpx_le_f32_e32 0, v{{[0-9]+}}
+; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]]
define amdgpu_ps void @vcc_implicit_def(float %arg13, float %arg14) {
%tmp0 = fcmp olt float %arg13, 0.000000e+00
%c1 = fcmp oge float %arg14, 0.0
@@ -30,28 +32,28 @@ define amdgpu_ps void @vcc_implicit_def(
ret void
}
-; SI-LABEL: {{^}}true:
-; SI-NEXT: %bb.
-; SI-NEXT: %bb.
-; SI-NEXT: s_endpgm
+; GCN-LABEL: {{^}}true:
+; GCN-NEXT: %bb.
+; GCN-NEXT: %bb.
+; GCN-NEXT: s_endpgm
define amdgpu_gs void @true() {
call void @llvm.amdgcn.kill(i1 true)
ret void
}
-; SI-LABEL: {{^}}false:
-; SI-NOT: v_cmpx
-; SI: s_mov_b64 exec, 0
+; GCN-LABEL: {{^}}false:
+; GCN-NOT: v_cmpx
+; GCN: s_mov_b64 exec, 0
define amdgpu_gs void @false() {
call void @llvm.amdgcn.kill(i1 false)
ret void
}
-; SI-LABEL: {{^}}and:
-; SI: v_cmp_lt_i32
-; SI: v_cmp_lt_i32
-; SI: s_or_b64 s[0:1]
-; SI: s_and_b64 exec, exec, s[0:1]
+; GCN-LABEL: {{^}}and:
+; GCN: v_cmp_lt_i32
+; GCN: v_cmp_lt_i32
+; GCN: s_or_b64 s[0:1]
+; GCN: s_and_b64 exec, exec, s[0:1]
define amdgpu_gs void @and(i32 %a, i32 %b, i32 %c, i32 %d) {
%c1 = icmp slt i32 %a, %b
%c2 = icmp slt i32 %c, %d
@@ -60,11 +62,11 @@ define amdgpu_gs void @and(i32 %a, i32 %
ret void
}
-; SI-LABEL: {{^}}andn2:
-; SI: v_cmp_lt_i32
-; SI: v_cmp_lt_i32
-; SI: s_xor_b64 s[0:1]
-; SI: s_andn2_b64 exec, exec, s[0:1]
+; GCN-LABEL: {{^}}andn2:
+; GCN: v_cmp_lt_i32
+; GCN: v_cmp_lt_i32
+; GCN: s_xor_b64 s[0:1]
+; GCN: s_andn2_b64 exec, exec, s[0:1]
define amdgpu_gs void @andn2(i32 %a, i32 %b, i32 %c, i32 %d) {
%c1 = icmp slt i32 %a, %b
%c2 = icmp slt i32 %c, %d
@@ -74,135 +76,140 @@ define amdgpu_gs void @andn2(i32 %a, i32
ret void
}
-; SI-LABEL: {{^}}oeq:
-; SI: v_cmpx_eq_f32
-; SI-NOT: s_and
+; GCN-LABEL: {{^}}oeq:
+; GCN: v_cmpx_eq_f32
+; GCN-NOT: s_and
define amdgpu_gs void @oeq(float %a) {
%c1 = fcmp oeq float %a, 0.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}ogt:
-; SI: v_cmpx_lt_f32
-; SI-NOT: s_and
+; GCN-LABEL: {{^}}ogt:
+; GCN: v_cmpx_lt_f32
+; GCN-NOT: s_and
define amdgpu_gs void @ogt(float %a) {
%c1 = fcmp ogt float %a, 0.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}oge:
-; SI: v_cmpx_le_f32
-; SI-NOT: s_and
+; GCN-LABEL: {{^}}oge:
+; GCN: v_cmpx_le_f32
+; GCN-NOT: s_and
define amdgpu_gs void @oge(float %a) {
%c1 = fcmp oge float %a, 0.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}olt:
-; SI: v_cmpx_gt_f32
-; SI-NOT: s_and
+; GCN-LABEL: {{^}}olt:
+; GCN: v_cmpx_gt_f32
+; GCN-NOT: s_and
define amdgpu_gs void @olt(float %a) {
%c1 = fcmp olt float %a, 0.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}ole:
-; SI: v_cmpx_ge_f32
-; SI-NOT: s_and
+; GCN-LABEL: {{^}}ole:
+; GCN: v_cmpx_ge_f32
+; GCN-NOT: s_and
define amdgpu_gs void @ole(float %a) {
%c1 = fcmp ole float %a, 0.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}one:
-; SI: v_cmpx_lg_f32
-; SI-NOT: s_and
+; GCN-LABEL: {{^}}one:
+; GCN: v_cmpx_lg_f32
+; GCN-NOT: s_and
define amdgpu_gs void @one(float %a) {
%c1 = fcmp one float %a, 0.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}ord:
+; GCN-LABEL: {{^}}ord:
; FIXME: This is absolutely unimportant, but we could use the cmpx variant here.
-; SI: v_cmp_o_f32
+; GCN: v_cmp_o_f32
define amdgpu_gs void @ord(float %a) {
%c1 = fcmp ord float %a, 0.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}uno:
+; GCN-LABEL: {{^}}uno:
; FIXME: This is absolutely unimportant, but we could use the cmpx variant here.
-; SI: v_cmp_u_f32
+; GCN: v_cmp_u_f32
define amdgpu_gs void @uno(float %a) {
%c1 = fcmp uno float %a, 0.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}ueq:
-; SI: v_cmpx_nlg_f32
-; SI-NOT: s_and
+; GCN-LABEL: {{^}}ueq:
+; GCN: v_cmpx_nlg_f32
+; GCN-NOT: s_and
define amdgpu_gs void @ueq(float %a) {
%c1 = fcmp ueq float %a, 0.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}ugt:
-; SI: v_cmpx_nge_f32
-; SI-NOT: s_and
+; GCN-LABEL: {{^}}ugt:
+; GCN: v_cmpx_nge_f32
+; GCN-NOT: s_and
define amdgpu_gs void @ugt(float %a) {
%c1 = fcmp ugt float %a, 0.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}uge:
+; GCN-LABEL: {{^}}uge:
; SI: v_cmpx_ngt_f32_e32 vcc, -1.0
-; SI-NOT: s_and
+; GFX10: v_cmpx_ngt_f32_e32 -1.0
+; GCN-NOT: s_and
define amdgpu_gs void @uge(float %a) {
%c1 = fcmp uge float %a, -1.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}ult:
+; GCN-LABEL: {{^}}ult:
; SI: v_cmpx_nle_f32_e32 vcc, -2.0
-; SI-NOT: s_and
+; GFX10: v_cmpx_nle_f32_e32 -2.0
+; GCN-NOT: s_and
define amdgpu_gs void @ult(float %a) {
%c1 = fcmp ult float %a, -2.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}ule:
+; GCN-LABEL: {{^}}ule:
; SI: v_cmpx_nlt_f32_e32 vcc, 2.0
-; SI-NOT: s_and
+; GFX10: v_cmpx_nlt_f32_e32 2.0
+; GCN-NOT: s_and
define amdgpu_gs void @ule(float %a) {
%c1 = fcmp ule float %a, 2.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}une:
+; GCN-LABEL: {{^}}une:
; SI: v_cmpx_neq_f32_e32 vcc, 0
-; SI-NOT: s_and
+; GFX10: v_cmpx_neq_f32_e32 0
+; GCN-NOT: s_and
define amdgpu_gs void @une(float %a) {
%c1 = fcmp une float %a, 0.0
call void @llvm.amdgcn.kill(i1 %c1)
ret void
}
-; SI-LABEL: {{^}}neg_olt:
+; GCN-LABEL: {{^}}neg_olt:
; SI: v_cmpx_ngt_f32_e32 vcc, 1.0
-; SI-NOT: s_and
+; GFX10: v_cmpx_ngt_f32_e32 1.0
+; GCN-NOT: s_and
define amdgpu_gs void @neg_olt(float %a) {
%c1 = fcmp olt float %a, 1.0
%c2 = xor i1 %c1, 1
@@ -210,11 +217,12 @@ define amdgpu_gs void @neg_olt(float %a)
ret void
}
-; SI-LABEL: {{^}}fcmp_x2:
+; GCN-LABEL: {{^}}fcmp_x2:
; FIXME: LLVM should be able to combine these fcmp opcodes.
; SI: v_cmp_lt_f32_e32 vcc, s{{[0-9]+}}, v0
-; SI: v_cndmask_b32
-; SI: v_cmpx_le_f32
+; GFX10: v_cmp_lt_f32_e32 vcc, 0x3e800000, v0
+; GCN: v_cndmask_b32
+; GCN: v_cmpx_le_f32
define amdgpu_ps void @fcmp_x2(float %a) #0 {
%ogt = fcmp nsz ogt float %a, 2.500000e-01
%k = select i1 %ogt, float -1.000000e+00, float 0.000000e+00
@@ -223,10 +231,10 @@ define amdgpu_ps void @fcmp_x2(float %a)
ret void
}
-; SI-LABEL: {{^}}wqm:
-; SI: v_cmp_neq_f32_e32 vcc, 0
-; SI: s_wqm_b64 s[0:1], vcc
-; SI: s_and_b64 exec, exec, s[0:1]
+; GCN-LABEL: {{^}}wqm:
+; GCN: v_cmp_neq_f32_e32 vcc, 0
+; GCN: s_wqm_b64 s[0:1], vcc
+; GCN: s_and_b64 exec, exec, s[0:1]
define amdgpu_ps void @wqm(float %a) {
%c1 = fcmp une float %a, 0.0
%c2 = call i1 @llvm.amdgcn.wqm.vote(i1 %c1)
@@ -235,27 +243,27 @@ define amdgpu_ps void @wqm(float %a) {
}
; This checks that we use the 64-bit encoding when the operand is a SGPR.
-; SI-LABEL: {{^}}test_sgpr:
-; SI: v_cmpx_ge_f32_e64
+; GCN-LABEL: {{^}}test_sgpr:
+; GCN: v_cmpx_ge_f32_e64
define amdgpu_ps void @test_sgpr(float inreg %a) #0 {
%c = fcmp ole float %a, 1.000000e+00
call void @llvm.amdgcn.kill(i1 %c) #1
ret void
}
-; SI-LABEL: {{^}}test_non_inline_imm_sgpr:
-; SI-NOT: v_cmpx_ge_f32_e64
+; GCN-LABEL: {{^}}test_non_inline_imm_sgpr:
+; GCN-NOT: v_cmpx_ge_f32_e64
define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 {
%c = fcmp ole float %a, 1.500000e+00
call void @llvm.amdgcn.kill(i1 %c) #1
ret void
}
-; SI-LABEL: {{^}}test_scc_liveness:
-; SI: v_cmp
-; SI: s_and_b64 exec
-; SI: s_cmp
-; SI: s_cbranch_scc
+; GCN-LABEL: {{^}}test_scc_liveness:
+; GCN: v_cmp
+; GCN: s_and_b64 exec
+; GCN: s_cmp
+; GCN: s_cbranch_scc
define amdgpu_ps void @test_scc_liveness() #0 {
main_body:
br label %loop3
Modified: llvm/trunk/test/CodeGen/AMDGPU/smem-war-hazard.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/smem-war-hazard.mir?rev=363190&r1=363189&r2=363190&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/smem-war-hazard.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/smem-war-hazard.mir Wed Jun 12 11:44:11 2019
@@ -1,4 +1,4 @@
-# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: hazard_smem_war
# GCN: S_LOAD_DWORD_IMM
Modified: llvm/trunk/test/CodeGen/AMDGPU/v_cndmask.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/v_cndmask.ll?rev=363190&r1=363189&r2=363190&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/v_cndmask.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/v_cndmask.ll Wed Jun 12 11:44:11 2019
@@ -1,6 +1,6 @@
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SIVI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,SIVI %s
-; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global,+WavefrontSize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s
declare i32 @llvm.amdgcn.workitem.id.x() #1
Modified: llvm/trunk/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir?rev=363190&r1=363189&r2=363190&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir Wed Jun 12 11:44:11 2019
@@ -1,4 +1,4 @@
-# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-insert-skips,post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64 -verify-machineinstrs -run-pass si-insert-skips,post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: hazard_vcmpx_smov_exec_lo
# GCN: $sgpr0 = S_MOV_B32 $exec_lo
Modified: llvm/trunk/test/MC/AMDGPU/expressions-gfx10.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/expressions-gfx10.s?rev=363190&r1=363189&r2=363190&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/expressions-gfx10.s (original)
+++ llvm/trunk/test/MC/AMDGPU/expressions-gfx10.s Wed Jun 12 11:44:11 2019
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64 -show-encoding %s | FileCheck %s --check-prefix=GFX10
i1=1
Added: llvm/trunk/test/MC/AMDGPU/vop3-literal.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop3-literal.s?rev=363190&view=auto
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/vop3-literal.s (added)
+++ llvm/trunk/test/MC/AMDGPU/vop3-literal.s Wed Jun 12 11:44:11 2019
@@ -0,0 +1,389 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX10 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX9 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX10-ERR %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX9-ERR %s
+
+v_bfe_u32 v0, 0x3039, v1, s1
+// GFX10: v_bfe_u32 v0, 0x3039, v1, s1 ; encoding: [0x00,0x00,0x48,0xd5,0xff,0x02,0x06,0x00,0x39,0x30,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_bfe_u32 v0, v1, 0x3039, s1
+// GFX10: v_bfe_u32 v0, v1, 0x3039, s1 ; encoding: [0x00,0x00,0x48,0xd5,0x01,0xff,0x05,0x00,0x39,0x30,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_bfe_u32 v0, v1, s1, 0x3039
+// GFX10: v_bfe_u32 v0, v1, s1, 0x3039 ; encoding: [0x00,0x00,0x48,0xd5,0x01,0x03,0xfc,0x03,0x39,0x30,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_bfe_u32 v0, 0x3039, 0x3039, s1
+// GFX10: v_bfe_u32 v0, 0x3039, 0x3039, s1 ; encoding: [0x00,0x00,0x48,0xd5,0xff,0xfe,0x05,0x00,0x39,0x30,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_bfe_u32 v0, 0x3039, s1, 0x3039
+// GFX10: v_bfe_u32 v0, 0x3039, s1, 0x3039 ; encoding: [0x00,0x00,0x48,0xd5,0xff,0x02,0xfc,0x03,0x39,0x30,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_bfe_u32 v0, v1, 0x3039, 0x3039
+// GFX10: v_bfe_u32 v0, v1, 0x3039, 0x3039 ; encoding: [0x00,0x00,0x48,0xd5,0x01,0xff,0xfd,0x03,0x39,0x30,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_bfe_u32 v0, 0x3039, 0x3039, 0x3039
+// GFX10: v_bfe_u32 v0, 0x3039, 0x3039, 0x3039 ; encoding: [0x00,0x00,0x48,0xd5,0xff,0xfe,0xfd,0x03,0x39,0x30,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_bfe_u32 v0, 0x3039, s1, 0x3038
+// GFX10-ERR: error: invalid literal operand
+// GFX9-ERR: error: invalid literal operand
+
+v_bfe_u32 v0, 0x3039, v1, v2
+// GFX10: v_bfe_u32 v0, 0x3039, v1, v2 ; encoding: [0x00,0x00,0x48,0xd5,0xff,0x02,0x0a,0x04,0x39,0x30,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_bfe_u32 v0, 0x3039, 0x12345, v2
+// GFX10-ERR: error: invalid literal operand
+// GFX9-ERR: error: invalid literal operand
+
+v_bfe_u32 v0, s1, 0x3039, s1
+// GFX10-ERR: v_bfe_u32 v0, s1, 0x3039, s1 ; encoding: [0x00,0x00,0x48,0xd5,0x01,0xfe,0x05,0x00,0x39,0x30,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_bfe_u32 v0, s1, 0x3039, s2
+// GFX10: error: invalid operand (violates constant bus restrictions)
+// GFX9-ERR: error: invalid literal operand
+
+v_bfm_b32_e64 v0, 0x3039, s1
+// GFX10: v_bfm_b32_e64 v0, 0x3039, s1 ; encoding: [0x00,0x00,0x63,0xd7,0xff,0x02,0x00,0x00,0x39,0x30,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_bfm_b32_e64 v0, 0x3039, v1
+// GFX10: v_bfm_b32_e64 v0, 0x3039, v1 ; encoding: [0x00,0x00,0x63,0xd7,0xff,0x02,0x02,0x00,0x39,0x30,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_bfm_b32_e64 v0, 0x3039, 0x3039
+// GFX10: v_bfm_b32_e64 v0, 0x3039, 0x3039 ; encoding: [0x00,0x00,0x63,0xd7,0xff,0xfe,0x01,0x00,0x39,0x30,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_bfm_b32_e64 v0, 0x3039, 0x3038
+// GFX10-ERR: error: invalid literal operand
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_f16 v1, 25.0, v2
+// GFX10: v_pk_add_f16 v1, 0x4e40, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x40,0x4e,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_f16 v1, 123456, v2
+// GFX10: v_pk_add_f16 v1, 0x1e240, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x40,0xe2,0x01,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_f16 v1, -200, v2
+// GFX10: v_pk_add_f16 v1, 0xffffff38, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x38,0xff,0xff,0xff]
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_f16 v1, 25.0, 25.0
+// GFX10: v_pk_add_f16 v1, 0x4e40, 0x4e40 ; encoding: [0x01,0x00,0x0f,0xcc,0xff,0xfe,0x01,0x18,0x40,0x4e,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_f16 v1, 25.0, 25.1
+// GFX10-ERR: error: invalid literal operand
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_u16 v1, -200, v2
+// GFX10: v_pk_add_u16 v1, 0xffffff38, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x38,0xff,0xff,0xff]
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_u16 v1, 64, v2
+// GFX10: v_pk_add_u16 v1, 64, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xc0,0x04,0x02,0x18]
+// GFX9: v_pk_add_u16 v1, 64, v2 ; encoding: [0x01,0x00,0x8a,0xd3,0xc0,0x04,0x02,0x18]
+
+v_pk_add_u16 v1, 65, v2
+// GFX10: v_pk_add_u16 v1, 0x41, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x41,0x00,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_u16 v1, -1, v2
+// GFX10: v_pk_add_u16 v1, -1, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xc1,0x04,0x02,0x18]
+// GFX9: v_pk_add_u16 v1, -1, v2 ; encoding: [0x01,0x00,0x8a,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_add_u16 v1, -5, v2
+// GFX10: v_pk_add_u16 v1, -5, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xc5,0x04,0x02,0x18]
+// GFX9: v_pk_add_u16 v1, -5, v2 ; encoding: [0x01,0x00,0x8a,0xd3,0xc5,0x04,0x02,0x18]
+
+v_pk_add_u16 v1, -100, v2
+// GFX10: v_pk_add_u16 v1, 0xffffff9c, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x9c,0xff,0xff,0xff]
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_u16 v1, -100, -100
+// GFX10: v_pk_add_u16 v1, 0xffffff9c, 0xffffff9c ; encoding: [0x01,0x00,0x0a,0xcc,0xff,0xfe,0x01,0x18,0x9c,0xff,0xff,0xff]
+// GFX9-ERR: error: invalid literal operand
+
+v_add_f32_e64 v1, neg(abs(0x123)), v3
+// GFX10: v_add_f32_e64 v1, -|0x123|, v3 ; encoding: [0x01,0x01,0x03,0xd5,0xff,0x06,0x02,0x20,0x23,0x01,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_add_f32_e64 v1, v3, neg(0x123)
+// GFX10: v_add_f32_e64 v1, v3, neg(0x123) ; encoding: [0x01,0x00,0x03,0xd5,0x03,0xff,0x01,0x40,0x23,0x01,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_add_f32_e64 v1, neg(abs(0x12345678)), neg(0x12345678)
+// GFX10: v_add_f32_e64 v1, -|0x12345678|, neg(0x12345678) ; encoding: [0x01,0x01,0x03,0xd5,0xff,0xfe,0x01,0x60,0x78,0x56,0x34,0x12]
+// GFX9-ERR: error: invalid literal operand
+
+v_add_f16_e64 v0, v0, 0xfe0b
+// GFX10: v_add_f16_e64 v0, v0, 0xfe0b ; encoding: [0x00,0x00,0x32,0xd5,0x00,0xff,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_add_f16_e64 v0, v0, neg(0xfe0b)
+// GFX10: v_add_f16_e64 v0, v0, neg(0xfe0b) ; encoding: [0x00,0x00,0x32,0xd5,0x00,0xff,0x01,0x40,0x0b,0xfe,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_add_f16_e64 v0, 0x3456, v0
+// GFX10: v_add_f16_e64 v0, 0x3456, v0 ; encoding: [0x00,0x00,0x32,0xd5,0xff,0x00,0x02,0x00,0x56,0x34,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_add_f16_e64 v0, 0xfe0b, neg(0xfe0b)
+// GFX10: v_add_f16_e64 v0, 0xfe0b, neg(0xfe0b) ; encoding: [0x00,0x00,0x32,0xd5,0xff,0xfe,0x01,0x40,0x0b,0xfe,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_add_f64 v[0:1], 1.23456, v[0:1]
+// GFX10: v_add_f64 v[0:1], 0x3ff3c0c1, v[0:1] ; encoding: [0x00,0x00,0x64,0xd5,0xff,0x00,0x02,0x00,0xc1,0xc0,0xf3,0x3f]
+// GFX9-ERR: error: invalid literal operand
+
+v_add_f64 v[0:1], v[0:1], -abs(1.23456)
+// GFX10: v_add_f64 v[0:1], v[0:1], -|0x3ff3c0c1| ; encoding: [0x00,0x02,0x64,0xd5,0x00,0xff,0x01,0x40,0xc1,0xc0,0xf3,0x3f]
+// GFX9-ERR: error: invalid literal operand
+
+v_add_f64 v[0:1], 1.23456, -abs(1.23456)
+// GFX10: v_add_f64 v[0:1], 0x3ff3c0c1, -|0x3ff3c0c1| ; encoding: [0x00,0x02,0x64,0xd5,0xff,0xfe,0x01,0x40,0xc1,0xc0,0xf3,0x3f]
+// GFX9-ERR: error: invalid literal operand
+
+v_add_f64 v[0:1], 1.23456, -abs(1.2345)
+// GFX10-ERR: error: invalid literal operand
+// GFX9-ERR: error: invalid literal operand
+
+v_max_i16_e64 v5, 0xfe0b, v2
+// GFX10: v_max_i16_e64 v5, 0xfe0b, v2 ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0x04,0x02,0x00,0x0b,0xfe,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_max_i16_e64 v5, v1, 0x123
+// GFX10: v_max_i16_e64 v5, v1, 0x123 ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x01,0x00,0x23,0x01,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_max_i16_e64 v5, 0x1234, 0x1234
+// GFX10: v_max_i16_e64 v5, 0x1234, 0x1234 ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0xfe,0x01,0x00,0x34,0x12,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_min3_i16 v5, 0xfe0b, v2, v3
+// GFX10: v_min3_i16 v5, 0xfe0b, v2, v3 ; encoding: [0x05,0x00,0x52,0xd7,0xff,0x04,0x0e,0x04,0x0b,0xfe,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_min3_i16 v5, v1, 0x1234, v3
+// GFX10: v_min3_i16 v5, v1, 0x1234, v3 ; encoding: [0x05,0x00,0x52,0xd7,0x01,0xff,0x0d,0x04,0x34,0x12,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_min3_i16 v5, v1, v2, 0x5678
+// GFX10: v_min3_i16 v5, v1, v2, 0x5678 ; encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xfe,0x03,0x78,0x56,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_min3_i16 v5, 0x5678, 0x5678, 0x5678
+// GFX10: v_min3_i16 v5, 0x5678, 0x5678, 0x5678 ; encoding: [0x05,0x00,0x52,0xd7,0xff,0xfe,0xfd,0x03,0x78,0x56,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_min3_i16 v5, 0x5678, 0x5679, 0x5678
+// GFX10-ERR: error: invalid literal operand
+// GFX9-ERR: error: invalid literal operand
+
+v_min3_i16 v5, 0x5678, 0x5678, 0x5679
+// GFX10-ERR: error: invalid literal operand
+// GFX9-ERR: error: invalid literal operand
+
+v_add_nc_u16 v5, 0xfe0b, v2
+// GFX10: v_add_nc_u16_e64 v5, 0xfe0b, v2 ; encoding: [0x05,0x00,0x03,0xd7,0xff,0x04,0x02,0x00,0x0b,0xfe,0x00,0x00]
+
+v_add_nc_u16 v5, v1, 0x1234
+// GFX10: v_add_nc_u16_e64 v5, v1, 0x1234 ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x01,0x00,0x34,0x12,0x00,0x00]
+
+v_add_nc_u16 v5, 0x1234, 0x1234
+// GFX10: v_add_nc_u16_e64 v5, 0x1234, 0x1234 ; encoding: [0x05,0x00,0x03,0xd7,0xff,0xfe,0x01,0x00,0x34,0x12,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, 0x3456, v2
+// GFX10: v_ashrrev_i16_e64 v5, 0x3456, v2 ; encoding: [0x05,0x00,0x08,0xd7,0xff,0x04,0x02,0x00,0x56,0x34,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_mad_u16 v5, 0xfe0b, v2, v3
+// GFX10: v_mad_u16 v5, 0xfe0b, v2, v3 ; encoding: [0x05,0x00,0x40,0xd7,0xff,0x04,0x0e,0x04,0x0b,0xfe,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_mad_u16 v5, v1, 0x1234, v3
+// GFX10: v_mad_u16 v5, v1, 0x1234, v3 ; encoding: [0x05,0x00,0x40,0xd7,0x01,0xff,0x0d,0x04,0x34,0x12,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_mad_u16 v5, v1, v2, 0x5678
+// GFX10: v_mad_u16 v5, v1, v2, 0x5678 ; encoding: [0x05,0x00,0x40,0xd7,0x01,0x05,0xfe,0x03,0x78,0x56,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_mad_u16 v5, 0x5678, 0x5678, 0x5678
+// GFX10: v_mad_u16 v5, 0x5678, 0x5678, 0x5678 ; encoding: [0x05,0x00,0x40,0xd7,0xff,0xfe,0xfd,0x03,0x78,0x56,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_mad_legacy_f32 v5, 0xaf123456, v2, v3
+// GFX10: v_mad_legacy_f32 v5, 0xaf123456, v2, v3 ; encoding: [0x05,0x00,0x40,0xd5,0xff,0x04,0x0e,0x04,0x56,0x34,0x12,0xaf]
+// GFX9-ERR: error: invalid literal operand
+
+v_mad_legacy_f32 v5, v1, 0xaf123456, v3
+// GFX10: v_mad_legacy_f32 v5, v1, 0xaf123456, v3 ; encoding: [0x05,0x00,0x40,0xd5,0x01,0xff,0x0d,0x04,0x56,0x34,0x12,0xaf]
+// GFX9-ERR: error: invalid literal operand
+
+v_mad_legacy_f32 v5, v1, v2, 0xaf123456
+// GFX10: v_mad_legacy_f32 v5, v1, v2, 0xaf123456 ; encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xfe,0x03,0x56,0x34,0x12,0xaf]
+// GFX9-ERR: error: invalid literal operand
+
+v_mad_legacy_f32 v5, 0xaf123456, 0xaf123456, 0xaf123456
+// GFX10: v_mad_legacy_f32 v5, 0xaf123456, 0xaf123456, 0xaf123456 ; encoding: [0x05,0x00,0x40,0xd5,0xff,0xfe,0xfd,0x03,0x56,0x34,0x12,0xaf]
+// GFX9-ERR: error: invalid literal operand
+
+v_cmp_f_i32_e64 s[10:11], 0xaf123456, v2
+// GFX10: v_cmp_f_i32_e64 s[10:11], 0xaf123456, v2 ; encoding: [0x0a,0x00,0x80,0xd4,0xff,0x04,0x02,0x00,0x56,0x34,0x12,0xaf]
+// GFX9-ERR: error: invalid literal operand
+
+v_cmp_f_i32_e64 s[10:11], v1, 0xaf123456
+// GFX10: v_cmp_f_i32_e64 s[10:11], v1, 0xaf123456 ; encoding: [0x0a,0x00,0x80,0xd4,0x01,0xff,0x01,0x00,0x56,0x34,0x12,0xaf]
+// GFX9-ERR: error: invalid literal operand
+
+v_cmp_f_i32_e64 s[10:11], 0xaf123456, 0xaf123456
+// GFX10: v_cmp_f_i32_e64 s[10:11], 0xaf123456, 0xaf123456 ; encoding: [0x0a,0x00,0x80,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// GFX9-ERR: error: invalid literal operand
+
+v_cmp_f_i32_e64 s[10:11], 0xaf123456, 0xaf123455
+// GFX10-ERR: error: invalid literal operand
+
+v_cmp_f_u64_e64 s[10:11], 0xaf123456, v[2:3]
+// GFX10: v_cmp_f_u64_e64 s[10:11], 0xaf123456, v[2:3] ; encoding: [0x0a,0x00,0xe0,0xd4,0xff,0x04,0x02,0x00,0x56,0x34,0x12,0xaf]
+// GFX9-ERR: error: invalid literal operand
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], 0x3f717273
+// GFX10: v_cmp_f_u64_e64 s[10:11], v[1:2], 0x3f717273 ; encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xff,0x01,0x00,0x73,0x72,0x71,0x3f]
+// GFX9-ERR: error: invalid literal operand
+
+v_cmp_f_u64_e64 s[10:11], 0x3f717273, 0x3f717273
+// GFX10: v_cmp_f_u64_e64 s[10:11], 0x3f717273, 0x3f717273 ; encoding: [0x0a,0x00,0xe0,0xd4,0xff,0xfe,0x01,0x00,0x73,0x72,0x71,0x3f]
+// GFX9-ERR: error: invalid literal operand
+
+v_cmpx_class_f32_e64 0xaf123456, v2
+// GFX10: v_cmpx_class_f32_e64 0xaf123456, v2 ; encoding: [0x00,0x00,0x98,0xd4,0xff,0x04,0x02,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f32_e64 v1, 0xaf123456
+// GFX10: v_cmpx_class_f32_e64 v1, 0xaf123456 ; encoding: [0x00,0x00,0x98,0xd4,0x01,0xff,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f32_e64 0xaf123456, 0xaf123456
+// GFX10: v_cmpx_class_f32_e64 0xaf123456, 0xaf123456 ; encoding: [0x00,0x00,0x98,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f32_e64 0xaf123456, 0xaf123455
+// GFX10-ERR: error: invalid literal operand
+
+v_cmpx_lt_i16_e64 v1, 0x3456
+// GFX10: v_cmpx_lt_i16_e64 v1, 0x3456 ; encoding: [0x00,0x00,0x99,0xd4,0x01,0xff,0x01,0x00,0x56,0x34,0x00,0x00]
+
+v_cmpx_lt_i16_e64 0x3456, v2
+// GFX10: v_cmpx_lt_i16_e64 0x3456, v2 ; encoding: [0x00,0x00,0x99,0xd4,0xff,0x04,0x02,0x00,0x56,0x34,0x00,0x00]
+
+v_cmpx_lt_i16_e64 0x3456, 0x3456
+// GFX10: v_cmpx_lt_i16_e64 0x3456, 0x3456 ; encoding: [0x00,0x00,0x99,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x00,0x00]
+
+v_cmpx_f_i64_e64 0xaf123456, v[2:3]
+// GFX10: v_cmpx_f_i64_e64 0xaf123456, v[2:3] ; encoding: [0x00,0x00,0xb0,0xd4,0xff,0x04,0x02,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_i64_e64 v[1:2], 0x3f717273
+// GFX10: v_cmpx_f_i64_e64 v[1:2], 0x3f717273 ; encoding: [0x00,0x00,0xb0,0xd4,0x01,0xff,0x01,0x00,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_i64_e64 0x3f717273, 0x3f717273
+// GFX10: v_cmpx_f_i64_e64 0x3f717273, 0x3f717273 ; encoding: [0x00,0x00,0xb0,0xd4,0xff,0xfe,0x01,0x00,0x73,0x72,0x71,0x3f]
+
+v_lshlrev_b64 v[5:6], 0xaf123456, v[2:3]
+// GFX10: v_lshlrev_b64 v[5:6], 0xaf123456, v[2:3] ; encoding: [0x05,0x00,0xff,0xd6,0xff,0x04,0x02,0x00,0x56,0x34,0x12,0xaf]
+// GFX9-ERR: error: invalid literal operand
+
+v_lshlrev_b64 v[5:6], v1, 0x3f717273
+// GFX10: v_lshlrev_b64 v[5:6], v1, 0x3f717273 ; encoding: [0x05,0x00,0xff,0xd6,0x01,0xff,0x01,0x00,0x73,0x72,0x71,0x3f]
+// GFX9-ERR: error: invalid literal operand
+
+v_lshlrev_b64 v[5:6], 0x3f717273, 0x3f717273
+// GFX10: v_lshlrev_b64 v[5:6], 0x3f717273, 0x3f717273 ; encoding: [0x05,0x00,0xff,0xd6,0xff,0xfe,0x01,0x00,0x73,0x72,0x71,0x3f]
+// GFX9-ERR: error: invalid literal operand
+
+v_fma_mix_f32 v5, 0x123, v2, v3
+// GFX10: v_fma_mix_f32 v5, 0x123, v2, v3 ; encoding: [0x05,0x00,0x20,0xcc,0xff,0x04,0x0e,0x04,0x23,0x01,0x00,0x00]
+
+v_fma_mix_f32 v5, v1, 0x7b, v3
+// GFX10: v_fma_mix_f32 v5, v1, 0x7b, v3 ; encoding: [0x05,0x00,0x20,0xcc,0x01,0xff,0x0d,0x04,0x7b,0x00,0x00,0x00]
+
+v_fma_mix_f32 v5, v1, v2, 0x1c8
+// GFX10: v_fma_mix_f32 v5, v1, v2, 0x1c8 ; encoding: [0x05,0x00,0x20,0xcc,0x01,0x05,0xfe,0x03,0xc8,0x01,0x00,0x00]
+
+v_fma_mix_f32 v5, 0x1c8a, v2, 0x1c8a
+// GFX10: v_fma_mix_f32 v5, 0x1c8a, v2, 0x1c8a ; encoding: [0x05,0x00,0x20,0xcc,0xff,0x04,0xfe,0x03,0x8a,0x1c,0x00,0x00]
+
+v_fma_mix_f32 v5, 0x1c8a, 0x1c8a, 0x1c8a
+// GFX10: v_fma_mix_f32 v5, 0x1c8a, 0x1c8a, 0x1c8a ; encoding: [0x05,0x00,0x20,0xcc,0xff,0xfe,0xfd,0x03,0x8a,0x1c,0x00,0x00]
+
+v_pk_add_f16 v5, 0xaf123456, v2
+// GFX10: v_pk_add_f16 v5, 0xaf123456, v2 ; encoding: [0x05,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x56,0x34,0x12,0xaf]
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_f16 v5, v1, 0x3f717273
+// GFX10: v_pk_add_f16 v5, v1, 0x3f717273 ; encoding: [0x05,0x00,0x0f,0xcc,0x01,0xff,0x01,0x18,0x73,0x72,0x71,0x3f]
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_f16 v5, 0x3f717273, 0x3f717273
+// GFX10: v_pk_add_f16 v5, 0x3f717273, 0x3f717273 ; encoding: [0x05,0x00,0x0f,0xcc,0xff,0xfe,0x01,0x18,0x73,0x72,0x71,0x3f]
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_i16 v5, 0x7b, v2
+// GFX10: v_pk_add_i16 v5, 0x7b, v2 ; encoding: [0x05,0x00,0x02,0xcc,0xff,0x04,0x02,0x18,0x7b,0x00,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_i16 v5, v1, 0x7b
+// GFX10: v_pk_add_i16 v5, v1, 0x7b ; encoding: [0x05,0x00,0x02,0xcc,0x01,0xff,0x01,0x18,0x7b,0x00,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_i16 v5, 0xab7b, 0xab7b
+// GFX10: v_pk_add_i16 v5, 0xab7b, 0xab7b ; encoding: [0x05,0x00,0x02,0xcc,0xff,0xfe,0x01,0x18,0x7b,0xab,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_pk_add_i16 v5, 0xab7b, 0xab7a
+// GFX10-ERR: error: invalid literal operand
+// GFX9-ERR: error: invalid literal operand
+
+v_div_fmas_f32 v5, v1, 0x123, v3
+// GFX10: v_div_fmas_f32 v5, v1, 0x123, v3 ; encoding: [0x05,0x00,0x6f,0xd5,0x01,0xff,0x0d,0x04,0x23,0x01,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_div_fmas_f32 v5, v1, 0x123, 0x123
+// GFX10: v_div_fmas_f32 v5, v1, 0x123, 0x123 ; encoding: [0x05,0x00,0x6f,0xd5,0x01,0xff,0xfd,0x03,0x23,0x01,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_div_fmas_f32 v5, 0x123, 0x123, 0x123
+// GFX10: v_div_fmas_f32 v5, 0x123, 0x123, 0x123 ; encoding: [0x05,0x00,0x6f,0xd5,0xff,0xfe,0xfd,0x03,0x23,0x01,0x00,0x00]
+// GFX9-ERR: error: invalid literal operand
+
+v_div_fmas_f64 v[5:6], 0x12345678, v[2:3], v[3:4]
+// GFX10: v_div_fmas_f64 v[5:6], 0x12345678, v[2:3], v[3:4] ; encoding: [0x05,0x00,0x70,0xd5,0xff,0x04,0x0e,0x04,0x78,0x56,0x34,0x12]
+// GFX9-ERR: error: invalid literal operand
+
+v_div_fmas_f64 v[5:6], 0x12345678, 0x12345678, 0x12345678
+// GFX10: v_div_fmas_f64 v[5:6], 0x12345678, 0x12345678, 0x12345678 ; encoding: [0x05,0x00,0x70,0xd5,0xff,0xfe,0xfd,0x03,0x78,0x56,0x34,0x12]
+// GFX9-ERR: error: invalid literal operand
+
+v_div_fmas_f64 v[5:6], v[1:2], 0x123457, 0x123456
+// GFX10-ERR: error: invalid literal operand
+// GFX9-ERR: error: invalid literal operand
+
+v_ldexp_f64 v[5:6], 0.12345, v2
+// GFX10: v_ldexp_f64 v[5:6], 0x3fbf9a6b, v2 ; encoding: [0x05,0x00,0x68,0xd5,0xff,0x04,0x02,0x00,0x6b,0x9a,0xbf,0x3f]
+// GFX9-ERR: error: invalid literal operand
+
+v_ldexp_f64 v[5:6], 0.12345, 0x3fbf9a6b
+// GFX10: v_ldexp_f64 v[5:6], 0x3fbf9a6b, 0x3fbf9a6b ; encoding: [0x05,0x00,0x68,0xd5,0xff,0xfe,0x01,0x00,0x6b,0x9a,0xbf,0x3f]
+// GFX9-ERR: error: invalid literal operand
+
+v_ldexp_f64 v[5:6], 0.12345, 0x3fbf9a6c
+// GFX10-ERR: error: invalid literal operand
+// GFX9-ERR: error: invalid literal operand
More information about the llvm-commits
mailing list