[PATCH] D63205: Virtualize TargetInstrInfo::getRegClass()

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added reviewers: kzhuravl, msearles, spatel, craig.topper, stoklund.
Herald added a subscriber: tpr.
rampitec added a child revision: D63204: [AMDGPU] gfx1010 core wave32 changes.

AMDGPU target needs to override getRegClass() used during
instruction selection. We now may have either 32 or 64 bit
conditional registers used in the same instructions. For
that purpose special SReg_1 register class is created which
is dynamically resolved to either SReg_64 or SGPR_32 depending
on the subtarget attributes.

See AMDGPU specific change D63204 <https://reviews.llvm.org/D63204> for the usage.


https://reviews.llvm.org/D63205

Files:
  include/llvm/CodeGen/TargetInstrInfo.h


Index: include/llvm/CodeGen/TargetInstrInfo.h
===================================================================
--- include/llvm/CodeGen/TargetInstrInfo.h
+++ include/llvm/CodeGen/TargetInstrInfo.h
@@ -80,6 +80,7 @@
 
   /// Given a machine instruction descriptor, returns the register
   /// class constraint for OpNum, or NULL.
+  virtual
   const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
                                          const TargetRegisterInfo *TRI,
                                          const MachineFunction &MF) const;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D63205.204288.patch
Type: text/x-patch
Size: 575 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190612/3ae498c4/attachment.bin>