[llvm] r363049 - [NFC] Fixed arm/aarch64 test
David Bolvansky via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 11 04:09:25 PDT 2019
Author: xbolva00
Date: Tue Jun 11 04:09:25 2019
New Revision: 363049
URL: http://llvm.org/viewvc/llvm-project?rev=363049&view=rev
Log:
[NFC] Fixed arm/aarch64 test
Modified:
llvm/trunk/test/CodeGen/AArch64/arm64-popcnt.ll
llvm/trunk/test/CodeGen/ARM/popcnt.ll
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-popcnt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-popcnt.ll?rev=363049&r1=363048&r2=363049&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-popcnt.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-popcnt.ll Tue Jun 11 04:09:25 2019
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; RUN: llc < %s -mtriple=aarch64-eabi -mattr -neon -aarch64-neon-syntax=apple | FileCheck -check-prefix=CHECK-NONEON %s
-; RUN: llc < %s -mtriple=armv8a -mattr=+neon | FileCheck %s -check-prefix=CHECK-ARM8A-NEON
define i32 @cnt32_advsimd(i32 %x) nounwind readnone {
; CHECK-LABEL: cnt32_advsimd:
@@ -28,27 +27,6 @@ define i32 @cnt32_advsimd(i32 %x) nounwi
; CHECK-NONEON-NEXT: mul w8, w8, w9
; CHECK-NONEON-NEXT: lsr w0, w8, #24
; CHECK-NONEON-NEXT: ret
-;
-; CHECK-ARM8A-NEON-LABEL: cnt32_advsimd:
-; CHECK-ARM8A-NEON: @ %bb.0:
-; CHECK-ARM8A-NEON-NEXT: movw r1, #21845
-; CHECK-ARM8A-NEON-NEXT: movt r1, #21845
-; CHECK-ARM8A-NEON-NEXT: and r1, r1, r0, lsr #1
-; CHECK-ARM8A-NEON-NEXT: sub r0, r0, r1
-; CHECK-ARM8A-NEON-NEXT: movw r1, #13107
-; CHECK-ARM8A-NEON-NEXT: movt r1, #13107
-; CHECK-ARM8A-NEON-NEXT: and r2, r0, r1
-; CHECK-ARM8A-NEON-NEXT: and r0, r1, r0, lsr #2
-; CHECK-ARM8A-NEON-NEXT: movw r1, #3855
-; CHECK-ARM8A-NEON-NEXT: add r0, r2, r0
-; CHECK-ARM8A-NEON-NEXT: movt r1, #3855
-; CHECK-ARM8A-NEON-NEXT: add r0, r0, r0, lsr #4
-; CHECK-ARM8A-NEON-NEXT: and r0, r0, r1
-; CHECK-ARM8A-NEON-NEXT: movw r1, #257
-; CHECK-ARM8A-NEON-NEXT: movt r1, #257
-; CHECK-ARM8A-NEON-NEXT: mul r0, r0, r1
-; CHECK-ARM8A-NEON-NEXT: lsr r0, r0, #24
-; CHECK-ARM8A-NEON-NEXT: bx lr
%cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
ret i32 %cnt
}
@@ -79,29 +57,6 @@ define i32 @cnt32_advsimd_2(<2 x i32> %x
; CHECK-NONEON-NEXT: mul w8, w8, w9
; CHECK-NONEON-NEXT: lsr w0, w8, #24
; CHECK-NONEON-NEXT: ret
-;
-; CHECK-ARM8A-NEON-LABEL: cnt32_advsimd_2:
-; CHECK-ARM8A-NEON: @ %bb.0:
-; CHECK-ARM8A-NEON-NEXT: vmov d16, r0, r1
-; CHECK-ARM8A-NEON-NEXT: movw r1, #21845
-; CHECK-ARM8A-NEON-NEXT: movt r1, #21845
-; CHECK-ARM8A-NEON-NEXT: vmov.32 r0, d16[0]
-; CHECK-ARM8A-NEON-NEXT: and r1, r1, r0, lsr #1
-; CHECK-ARM8A-NEON-NEXT: sub r0, r0, r1
-; CHECK-ARM8A-NEON-NEXT: movw r1, #13107
-; CHECK-ARM8A-NEON-NEXT: movt r1, #13107
-; CHECK-ARM8A-NEON-NEXT: and r2, r0, r1
-; CHECK-ARM8A-NEON-NEXT: and r0, r1, r0, lsr #2
-; CHECK-ARM8A-NEON-NEXT: movw r1, #3855
-; CHECK-ARM8A-NEON-NEXT: add r0, r2, r0
-; CHECK-ARM8A-NEON-NEXT: movt r1, #3855
-; CHECK-ARM8A-NEON-NEXT: add r0, r0, r0, lsr #4
-; CHECK-ARM8A-NEON-NEXT: and r0, r0, r1
-; CHECK-ARM8A-NEON-NEXT: movw r1, #257
-; CHECK-ARM8A-NEON-NEXT: movt r1, #257
-; CHECK-ARM8A-NEON-NEXT: mul r0, r0, r1
-; CHECK-ARM8A-NEON-NEXT: lsr r0, r0, #24
-; CHECK-ARM8A-NEON-NEXT: bx lr
%1 = extractelement <2 x i32> %x, i64 0
%2 = tail call i32 @llvm.ctpop.i32(i32 %1)
ret i32 %2
@@ -131,38 +86,6 @@ define i64 @cnt64_advsimd(i64 %x) nounwi
; CHECK-NONEON-NEXT: mul x8, x8, x9
; CHECK-NONEON-NEXT: lsr x0, x8, #56
; CHECK-NONEON-NEXT: ret
-;
-; CHECK-ARM8A-NEON-LABEL: cnt64_advsimd:
-; CHECK-ARM8A-NEON: @ %bb.0:
-; CHECK-ARM8A-NEON-NEXT: push {r11, lr}
-; CHECK-ARM8A-NEON-NEXT: movw r12, #21845
-; CHECK-ARM8A-NEON-NEXT: movw lr, #3855
-; CHECK-ARM8A-NEON-NEXT: movt r12, #21845
-; CHECK-ARM8A-NEON-NEXT: and r3, r12, r0, lsr #1
-; CHECK-ARM8A-NEON-NEXT: sub r0, r0, r3
-; CHECK-ARM8A-NEON-NEXT: movw r3, #13107
-; CHECK-ARM8A-NEON-NEXT: movt r3, #13107
-; CHECK-ARM8A-NEON-NEXT: and r2, r0, r3
-; CHECK-ARM8A-NEON-NEXT: and r0, r3, r0, lsr #2
-; CHECK-ARM8A-NEON-NEXT: movt lr, #3855
-; CHECK-ARM8A-NEON-NEXT: add r0, r2, r0
-; CHECK-ARM8A-NEON-NEXT: and r2, r12, r1, lsr #1
-; CHECK-ARM8A-NEON-NEXT: sub r1, r1, r2
-; CHECK-ARM8A-NEON-NEXT: and r2, r1, r3
-; CHECK-ARM8A-NEON-NEXT: add r0, r0, r0, lsr #4
-; CHECK-ARM8A-NEON-NEXT: and r1, r3, r1, lsr #2
-; CHECK-ARM8A-NEON-NEXT: and r0, r0, lr
-; CHECK-ARM8A-NEON-NEXT: add r1, r2, r1
-; CHECK-ARM8A-NEON-NEXT: movw r2, #257
-; CHECK-ARM8A-NEON-NEXT: movt r2, #257
-; CHECK-ARM8A-NEON-NEXT: add r1, r1, r1, lsr #4
-; CHECK-ARM8A-NEON-NEXT: mul r0, r0, r2
-; CHECK-ARM8A-NEON-NEXT: and r1, r1, lr
-; CHECK-ARM8A-NEON-NEXT: mul r1, r1, r2
-; CHECK-ARM8A-NEON-NEXT: lsr r0, r0, #24
-; CHECK-ARM8A-NEON-NEXT: add r0, r0, r1, lsr #24
-; CHECK-ARM8A-NEON-NEXT: mov r1, #0
-; CHECK-ARM8A-NEON-NEXT: pop {r11, pc}
%cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
ret i64 %cnt
}
@@ -202,27 +125,6 @@ define i32 @cnt32(i32 %x) nounwind readn
; CHECK-NONEON-NEXT: mul w8, w8, w9
; CHECK-NONEON-NEXT: lsr w0, w8, #24
; CHECK-NONEON-NEXT: ret
-;
-; CHECK-ARM8A-NEON-LABEL: cnt32:
-; CHECK-ARM8A-NEON: @ %bb.0:
-; CHECK-ARM8A-NEON-NEXT: movw r1, #21845
-; CHECK-ARM8A-NEON-NEXT: movt r1, #21845
-; CHECK-ARM8A-NEON-NEXT: and r1, r1, r0, lsr #1
-; CHECK-ARM8A-NEON-NEXT: sub r0, r0, r1
-; CHECK-ARM8A-NEON-NEXT: movw r1, #13107
-; CHECK-ARM8A-NEON-NEXT: movt r1, #13107
-; CHECK-ARM8A-NEON-NEXT: and r2, r0, r1
-; CHECK-ARM8A-NEON-NEXT: and r0, r1, r0, lsr #2
-; CHECK-ARM8A-NEON-NEXT: movw r1, #3855
-; CHECK-ARM8A-NEON-NEXT: add r0, r2, r0
-; CHECK-ARM8A-NEON-NEXT: movt r1, #3855
-; CHECK-ARM8A-NEON-NEXT: add r0, r0, r0, lsr #4
-; CHECK-ARM8A-NEON-NEXT: and r0, r0, r1
-; CHECK-ARM8A-NEON-NEXT: movw r1, #257
-; CHECK-ARM8A-NEON-NEXT: movt r1, #257
-; CHECK-ARM8A-NEON-NEXT: mul r0, r0, r1
-; CHECK-ARM8A-NEON-NEXT: lsr r0, r0, #24
-; CHECK-ARM8A-NEON-NEXT: bx lr
%cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
ret i32 %cnt
}
@@ -259,38 +161,6 @@ define i64 @cnt64(i64 %x) nounwind readn
; CHECK-NONEON-NEXT: mul x8, x8, x9
; CHECK-NONEON-NEXT: lsr x0, x8, #56
; CHECK-NONEON-NEXT: ret
-;
-; CHECK-ARM8A-NEON-LABEL: cnt64:
-; CHECK-ARM8A-NEON: @ %bb.0:
-; CHECK-ARM8A-NEON-NEXT: push {r11, lr}
-; CHECK-ARM8A-NEON-NEXT: movw r12, #21845
-; CHECK-ARM8A-NEON-NEXT: movw lr, #3855
-; CHECK-ARM8A-NEON-NEXT: movt r12, #21845
-; CHECK-ARM8A-NEON-NEXT: and r3, r12, r0, lsr #1
-; CHECK-ARM8A-NEON-NEXT: sub r0, r0, r3
-; CHECK-ARM8A-NEON-NEXT: movw r3, #13107
-; CHECK-ARM8A-NEON-NEXT: movt r3, #13107
-; CHECK-ARM8A-NEON-NEXT: and r2, r0, r3
-; CHECK-ARM8A-NEON-NEXT: and r0, r3, r0, lsr #2
-; CHECK-ARM8A-NEON-NEXT: movt lr, #3855
-; CHECK-ARM8A-NEON-NEXT: add r0, r2, r0
-; CHECK-ARM8A-NEON-NEXT: and r2, r12, r1, lsr #1
-; CHECK-ARM8A-NEON-NEXT: sub r1, r1, r2
-; CHECK-ARM8A-NEON-NEXT: and r2, r1, r3
-; CHECK-ARM8A-NEON-NEXT: add r0, r0, r0, lsr #4
-; CHECK-ARM8A-NEON-NEXT: and r1, r3, r1, lsr #2
-; CHECK-ARM8A-NEON-NEXT: and r0, r0, lr
-; CHECK-ARM8A-NEON-NEXT: add r1, r2, r1
-; CHECK-ARM8A-NEON-NEXT: movw r2, #257
-; CHECK-ARM8A-NEON-NEXT: movt r2, #257
-; CHECK-ARM8A-NEON-NEXT: add r1, r1, r1, lsr #4
-; CHECK-ARM8A-NEON-NEXT: mul r0, r0, r2
-; CHECK-ARM8A-NEON-NEXT: and r1, r1, lr
-; CHECK-ARM8A-NEON-NEXT: mul r1, r1, r2
-; CHECK-ARM8A-NEON-NEXT: lsr r0, r0, #24
-; CHECK-ARM8A-NEON-NEXT: add r0, r0, r1, lsr #24
-; CHECK-ARM8A-NEON-NEXT: mov r1, #0
-; CHECK-ARM8A-NEON-NEXT: pop {r11, pc}
%cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
ret i64 %cnt
}
@@ -323,20 +193,6 @@ define i32 @ctpop_eq_one(i64 %x) nounwin
; CHECK-NONEON-NEXT: cmp x8, #1 // =1
; CHECK-NONEON-NEXT: cset w0, eq
; CHECK-NONEON-NEXT: ret
-;
-; CHECK-ARM8A-NEON-LABEL: ctpop_eq_one:
-; CHECK-ARM8A-NEON: @ %bb.0:
-; CHECK-ARM8A-NEON-NEXT: subs r2, r0, #1
-; CHECK-ARM8A-NEON-NEXT: sbc r3, r1, #0
-; CHECK-ARM8A-NEON-NEXT: and r2, r0, r2
-; CHECK-ARM8A-NEON-NEXT: and r3, r1, r3
-; CHECK-ARM8A-NEON-NEXT: orrs r0, r0, r1
-; CHECK-ARM8A-NEON-NEXT: orr r2, r2, r3
-; CHECK-ARM8A-NEON-NEXT: movwne r0, #1
-; CHECK-ARM8A-NEON-NEXT: clz r2, r2
-; CHECK-ARM8A-NEON-NEXT: lsr r2, r2, #5
-; CHECK-ARM8A-NEON-NEXT: and r0, r0, r2
-; CHECK-ARM8A-NEON-NEXT: bx lr
%count = tail call i64 @llvm.ctpop.i64(i64 %x)
%cmp = icmp eq i64 %count, 1
%conv = zext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/ARM/popcnt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/popcnt.ll?rev=363049&r1=363048&r2=363049&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/popcnt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/popcnt.ll Tue Jun 11 04:09:25 2019
@@ -281,6 +281,28 @@ define <4 x i32> @vclsQs32(<4 x i32>* %A
ret <4 x i32> %tmp2
}
+define i32 @ctpop_eq_one(i64 %x) nounwind readnone {
+; CHECK-LABEL: ctpop_eq_one:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: subs r2, r0, #1
+; CHECK-NEXT: sbc r3, r1, #0
+; CHECK-NEXT: and r2, r0, r2
+; CHECK-NEXT: and r3, r1, r3
+; CHECK-NEXT: orr r2, r2, r3
+; CHECK-NEXT: rsbs r3, r2, #0
+; CHECK-NEXT: adc r2, r2, r3
+; CHECK-NEXT: orrs r0, r0, r1
+; CHECK-NEXT: movne r0, #1
+; CHECK-NEXT: and r0, r0, r2
+; CHECK-NEXT: mov pc, lr
+ %count = tail call i64 @llvm.ctpop.i64(i64 %x)
+ %cmp = icmp eq i64 %count, 1
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+declare i64 @llvm.ctpop.i64(i64) nounwind readnone
+
declare <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8>) nounwind readnone
declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) nounwind readnone
declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) nounwind readnone
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