[PATCH] D63079: [PowerPC][HTM] Fix $zero is not a GPRC register for builtin_ttest

[Jinsong Ji via Phabricator via llvm-commits]

jsji created this revision.
jsji added reviewers: kbarton, nemanjai, hfinkel, wuzish.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

This was found during HTM cleanup.
Adding a test for builtin_ttest would expose following issue.

  - Bad machine code: Illegal physical register for instruction ***
- function:    test10
- basic block: %bb.0 entry (0xf0e57497b58)
- instruction: %5:crrc0 = TABORTWCI 0, $zero, 0
- operand 2:   $zero

$zero is not a GPRC register.
LLVM ERROR: Found 1 machine code errors.


Repository:
  rL LLVM

https://reviews.llvm.org/D63079

Files:
  llvm/lib/Target/PowerPC/PPCInstrHTM.td
  llvm/test/CodeGen/PowerPC/htm.ll


Index: llvm/test/CodeGen/PowerPC/htm.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/htm.ll
+++ llvm/test/CodeGen/PowerPC/htm.ll
@@ -130,16 +130,19 @@
   %1 = tail call i32 @llvm.ppc.treclaim(i32 5)
   %2 = tail call i32 @llvm.ppc.trechkpt()
   %3 = tail call i32 @llvm.ppc.tsr(i32 1)
+  %4 = tail call i64 @llvm.ppc.ttest()
   ret void
 ; CHECK-LABEL: @test10
 ; CHECK: tcheck [[REG1:[0-9]+]] 
 ; CHECK: treclaim. [[REG2:[0-9]+]] 
 ; CHECK: trechkpt. 
 ; CHECK: tsr.  1
+; CHECK: tabortwci. 0, {{[0-9]+}}, 0
 }
 
 declare i32 @llvm.ppc.tcheck()
 declare i32 @llvm.ppc.treclaim(i32)
 declare i32 @llvm.ppc.trechkpt()
 declare i32 @llvm.ppc.tsr(i32)
+declare i64 @llvm.ppc.ttest()
 
Index: llvm/lib/Target/PowerPC/PPCInstrHTM.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrHTM.td
+++ llvm/lib/Target/PowerPC/PPCInstrHTM.td
@@ -164,6 +164,6 @@
           (TSR 0)>;
 
 def : Pat<(i64 (int_ppc_ttest)),
-          (RLDICL (i64 (COPY (TABORTWCI 0, ZERO, 0))), 36, 28)>;
+          (RLDICL (i64 (COPY (TABORTWCI 0, (LI 0), 0))), 36, 28)>;
 
 } // [HasHTM]


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