[llvm] r362898 - [X86] NFCI : Comment updation for EVEX to VEX translation.

[Jatin Bhateja via llvm-commits]

Author: jbhateja
Date: Sun Jun  9 02:59:26 2019
New Revision: 362898

URL: http://llvm.org/viewvc/llvm-project?rev=362898&view=rev
Log:
[X86] NFCI : Comment updation for EVEX to VEX translation.

Reviewers: llvm-commits, jbhateja

Reviewed By: jbhateja

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63055

Modified:
    llvm/trunk/lib/Target/X86/X86EvexToVex.cpp

Modified: llvm/trunk/lib/Target/X86/X86EvexToVex.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86EvexToVex.cpp?rev=362898&r1=362897&r2=362898&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86EvexToVex.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86EvexToVex.cpp Sun Jun  9 02:59:26 2019
@@ -12,9 +12,9 @@
 /// are encoded using the EVEX prefix and if possible replaces them by their
 /// corresponding VEX encoding which is usually shorter by 2 bytes.
 /// EVEX instructions may be encoded via the VEX prefix when the AVX-512
-/// instruction has a corresponding AVX/AVX2 opcode and when it does not
-/// use the xmm or the mask registers or xmm/ymm registers with indexes
-/// higher than 15.
+/// instruction has a corresponding AVX/AVX2 opcode, when vector length 
+/// accessed by instruction is less than 512 bits and when it does not use 
+//  the xmm or the mask registers or xmm/ymm registers with indexes higher than 15.
 /// The pass applies code reduction on the generated code for AVX-512 instrs.
 //
 //===----------------------------------------------------------------------===//