[llvm] r362689 - [MIPS GlobalISel] Select fpext and fptrunc
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 6 02:16:58 PDT 2019
Author: petar.avramovic
Date: Thu Jun 6 02:16:58 2019
New Revision: 362689
URL: http://llvm.org/viewvc/llvm-project?rev=362689&view=rev
Log:
[MIPS GlobalISel] Select fpext and fptrunc
Select G_FPEXT and G_FPTRUNC for MIPS32.
Differential Revision: https://reviews.llvm.org/D62902
Added:
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fpext_and_fptrunc.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fpext_and_fptrunc.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir
Modified:
llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp
Modified: llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp?rev=362689&r1=362688&r2=362689&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp Thu Jun 6 02:16:58 2019
@@ -104,6 +104,12 @@ MipsLegalizerInfo::MipsLegalizerInfo(con
getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR})
.libcallFor({s32, s64});
+ getActionDefinitionsBuilder(G_FPEXT)
+ .legalFor({{s64, s32}});
+
+ getActionDefinitionsBuilder(G_FPTRUNC)
+ .legalFor({{s32, s64}});
+
computeTables();
verify(*ST.getInstrInfo());
}
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp?rev=362689&r1=362688&r2=362689&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp Thu Jun 6 02:16:58 2019
@@ -160,6 +160,14 @@ MipsRegisterBankInfo::getInstrMapping(co
FPRValueMapping, FPRValueMapping});
break;
}
+ case G_FPEXT:
+ OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::DPRIdx],
+ &Mips::ValueMappings[Mips::SPRIdx]});
+ break;
+ case G_FPTRUNC:
+ OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::SPRIdx],
+ &Mips::ValueMappings[Mips::DPRIdx]});
+ break;
case G_CONSTANT:
case G_FRAME_INDEX:
case G_GLOBAL_VALUE:
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fpext_and_fptrunc.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fpext_and_fptrunc.mir?rev=362689&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fpext_and_fptrunc.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fpext_and_fptrunc.mir Thu Jun 6 02:16:58 2019
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+ define void @fpext() {entry: ret void}
+ define void @fptrunc() {entry: ret void}
+
+...
+---
+name: fpext
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12
+
+ ; FP32-LABEL: name: fpext
+ ; FP32: liveins: $f12
+ ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+ ; FP32: [[CVT_D32_S:%[0-9]+]]:afgr64 = CVT_D32_S [[COPY]]
+ ; FP32: $d0 = COPY [[CVT_D32_S]]
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: fpext
+ ; FP64: liveins: $f12
+ ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+ ; FP64: [[CVT_D64_S:%[0-9]+]]:fgr64 = CVT_D64_S [[COPY]]
+ ; FP64: $d0 = COPY [[CVT_D64_S]]
+ ; FP64: RetRA implicit $d0
+ %0:fprb(s32) = COPY $f12
+ %1:fprb(s64) = G_FPEXT %0(s32)
+ $d0 = COPY %1(s64)
+ RetRA implicit $d0
+
+...
+---
+name: fptrunc
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6
+
+ ; FP32-LABEL: name: fptrunc
+ ; FP32: liveins: $d6
+ ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
+ ; FP32: [[CVT_S_D32_:%[0-9]+]]:fgr32 = CVT_S_D32 [[COPY]]
+ ; FP32: $f0 = COPY [[CVT_S_D32_]]
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: fptrunc
+ ; FP64: liveins: $d6
+ ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
+ ; FP64: [[CVT_S_D64_:%[0-9]+]]:fgr32 = CVT_S_D64 [[COPY]]
+ ; FP64: $f0 = COPY [[CVT_S_D64_]]
+ ; FP64: RetRA implicit $f0
+ %0:fprb(s64) = COPY $d6
+ %1:fprb(s32) = G_FPTRUNC %0(s64)
+ $f0 = COPY %1(s32)
+ RetRA implicit $f0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fpext_and_fptrunc.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fpext_and_fptrunc.mir?rev=362689&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fpext_and_fptrunc.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fpext_and_fptrunc.mir Thu Jun 6 02:16:58 2019
@@ -0,0 +1,61 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+ define void @fpext() {entry: ret void}
+ define void @fptrunc() {entry: ret void}
+
+...
+---
+name: fpext
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12
+
+ ; FP32-LABEL: name: fpext
+ ; FP32: liveins: $f12
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[COPY]](s32)
+ ; FP32: $d0 = COPY [[FPEXT]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: fpext
+ ; FP64: liveins: $f12
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[COPY]](s32)
+ ; FP64: $d0 = COPY [[FPEXT]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s32) = COPY $f12
+ %1:_(s64) = G_FPEXT %0(s32)
+ $d0 = COPY %1(s64)
+ RetRA implicit $d0
+
+...
+---
+name: fptrunc
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6
+
+ ; FP32-LABEL: name: fptrunc
+ ; FP32: liveins: $d6
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[COPY]](s64)
+ ; FP32: $f0 = COPY [[FPTRUNC]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: fptrunc
+ ; FP64: liveins: $d6
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[COPY]](s64)
+ ; FP64: $f0 = COPY [[FPTRUNC]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s64) = COPY $d6
+ %1:_(s32) = G_FPTRUNC %0(s64)
+ $f0 = COPY %1(s32)
+ RetRA implicit $f0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll?rev=362689&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll Thu Jun 6 02:16:58 2019
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
+
+define double @fpext(float %a) {
+; MIPS32-LABEL: fpext:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: cvt.d.s $f0, $f12
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %conv = fpext float %a to double
+ ret double %conv
+}
+
+define float @fptrunc(double %a) {
+; MIPS32-LABEL: fptrunc:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: cvt.s.d $f0, $f12
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %conv = fptrunc double %a to float
+ ret float %conv
+}
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir?rev=362689&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir Thu Jun 6 02:16:58 2019
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+ define void @fpext() {entry: ret void}
+ define void @fptrunc() {entry: ret void}
+
+...
+---
+name: fpext
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12
+
+ ; FP32-LABEL: name: fpext
+ ; FP32: liveins: $f12
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP32: [[FPEXT:%[0-9]+]]:fprb(s64) = G_FPEXT [[COPY]](s32)
+ ; FP32: $d0 = COPY [[FPEXT]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: fpext
+ ; FP64: liveins: $f12
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP64: [[FPEXT:%[0-9]+]]:fprb(s64) = G_FPEXT [[COPY]](s32)
+ ; FP64: $d0 = COPY [[FPEXT]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s32) = COPY $f12
+ %1:_(s64) = G_FPEXT %0(s32)
+ $d0 = COPY %1(s64)
+ RetRA implicit $d0
+
+...
+---
+name: fptrunc
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6
+
+ ; FP32-LABEL: name: fptrunc
+ ; FP32: liveins: $d6
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP32: [[FPTRUNC:%[0-9]+]]:fprb(s32) = G_FPTRUNC [[COPY]](s64)
+ ; FP32: $f0 = COPY [[FPTRUNC]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: fptrunc
+ ; FP64: liveins: $d6
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP64: [[FPTRUNC:%[0-9]+]]:fprb(s32) = G_FPTRUNC [[COPY]](s64)
+ ; FP64: $f0 = COPY [[FPTRUNC]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s64) = COPY $d6
+ %1:_(s32) = G_FPTRUNC %0(s64)
+ $f0 = COPY %1(s32)
+ RetRA implicit $f0
+
+...
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