[PATCH] D62857: [RISCV] Prevent hoisting some adds after shifts

[Alex Bradbury via Phabricator via llvm-commits]

asb added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:860
+      APInt C2Int = C2->getAPIntValue();
+      if (C1Int.isSignedIntN(64) && C2Int.isSignedIntN(64)) {
+        RISCVMatInt::InstSeq C1Seq;
----------------
I was actually thinking it might be better to define getIntImmCost for RISC-V (which at least initially uses generateInstSeq, even if that might result in a little wasted work), then call that from here (that change might affect codegen in other areas, but should be an improvement). Arguably the introduction of getIntImmCost could make sense as a separate patch (that this one depends on), if a sensible standalone test case is straight forward.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62857/new/

https://reviews.llvm.org/D62857