[PATCH] D62900: [RISCV] Support Bit-Preserving FP in F/D Extensions

[Sam Elliott via Phabricator via llvm-commits]

lenary created this revision.
lenary added reviewers: asb, luismarques.
Herald added subscribers: llvm-commits, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.

This allows some integer bitwise operations to instead be performed by
hardware fp instructions. This is correct because the RISC-V spec
requires the F and D extensions to use the IEEE-754 standard
representation, and fp register loads and stores to be bit-preserving.

This is tested against the soft-float ABI, but with hardware float
extensions enabled, so that the tests also ensure the optimisation also
fires in this case.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D62900

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D62900.203135.patch
Type: text/x-patch
Size: 13689 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190605/b1442a2a/attachment.bin>