[PATCH] D62871: [Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: RKSimon, efriedma, t.p.northover, craig.topper, spatel, arsenm.
lebedev.ri added a project: LLVM.
Herald added subscribers: jsji, kristof.beyls, tpr, javed.absar, nhaehnle, wdng, jvesely, nemanjai.

This was originally reported in D62818 <https://reviews.llvm.org/D62818>.
https://rise4fun.com/Alive/oPH

InstCombine does the opposite fold, in hope that `C l>>/<< Y` expression
will be hoisted out of a loop if `Y` is invariant and `X` is not.
But as it is seen from the diffs here, if it didn't get hoisted,
the produced assembly is almost universally worse.

Much like with my recent "hoist add/sub by/from const" patches, 
we should get almost universal win if we hoist constant,
there is almost always an "and/test by imm" instruction,
but "shift of imm" not so much, so we may avoid having to
materialize the immediate, and thus need one less register.
And since we now shift not by constant, but by something else,
the live-range of that something else may reduce.

Special care needs to be applied not to disturb x86 `BT` / hexagon `tstbit`
instruction pattern. And to not get into endless combine loop.

>From what **i** can tell,

- PPC changes are all good
- AMDGPU neutral
- AArch64 good except vectors (pattern with `lshr` improves, but `shl` symmetrically degrades)
- ARM all good, at least in general?
- X86 look ok, the immediate gets encoded int `test` instruction (vectors are a mess regardless)


Repository:
  rL LLVM

https://reviews.llvm.org/D62871

Files:
  include/llvm/CodeGen/TargetLowering.h
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  lib/Target/Hexagon/HexagonISelLowering.h
  lib/Target/X86/X86ISelLowering.h
  test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
  test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
  test/CodeGen/AMDGPU/commute-shifts.ll
  test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
  test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
  test/CodeGen/PowerPC/shift-cmp.ll
  test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
  test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

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