[PATCH] D62864: AMDGPU: Don't fix emergency stack slot at offset 0

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, scott.linder.
Herald added subscribers: arphaman, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, qcolombet.

This forced the caller to be aware of this, which is an ugly ABI
feature.

      

Partially reverts r295877. The original reasons for doing this are
mostly fixed. Alloca is now in a non-0 address space, so it should be
OK to have 0 as a valid pointer. Since we treat the absolute address
as the pointer value, this part only really needed to apply to
kernels.

      

Since r357093, we avoid the need to increment/decrement the offset
register in more cases, and since r354816 the scavenger can fail
without spilling, so it's less critical that we try to avoid an offset
that fits in the MUBUF offset.

      

Restrict to callable functions for now to split this into 2 steps to
limit thte number of test updates and in case anything breaks.


https://reviews.llvm.org/D62864

Files:
  lib/Target/AMDGPU/SIFrameLowering.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  test/CodeGen/AMDGPU/byval-frame-setup.ll
  test/CodeGen/AMDGPU/call-argument-types.ll
  test/CodeGen/AMDGPU/callee-frame-setup.ll
  test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
  test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
  test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
  test/CodeGen/AMDGPU/frame-index-elimination.ll
  test/CodeGen/AMDGPU/function-args.ll
  test/CodeGen/AMDGPU/load-hi16.ll
  test/CodeGen/AMDGPU/load-lo16.ll
  test/CodeGen/AMDGPU/multi-dword-vgpr-spill.ll
  test/CodeGen/AMDGPU/nested-calls.ll
  test/CodeGen/AMDGPU/sibling-call.ll
  test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
  test/CodeGen/AMDGPU/spill-offset-calculation.ll
  test/CodeGen/AMDGPU/stack-realign.ll
  test/CodeGen/AMDGPU/store-hi16.ll

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