[PATCH] D62857: [RISCV] Prevent hoisting some adds after shifts

[Sam Elliott via Phabricator via llvm-commits]

lenary created this revision.
lenary added reviewers: asb, luismarques, efriedma.
Herald added subscribers: llvm-commits, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya.
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On RISC-V, materialising the large (shifted) constant produced for the
new add uses an extra register, and takes several instructions. It is
more efficient to perform the add before the shift if the constant to be
added fits into an immediate.

This is potentially useful to other targets, and might in future be done
within the target-independent part of DAGCombine.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D62857

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/add-before-shl.ll

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