[PATCH] D62818: [InstCombine] Allow ((X << Y) & SignMask) != 0 to be optimized as (X << Y) s< 0.

[Huihui Zhang via Phabricator via llvm-commits]

huihuiz added a comment.

For thumb target, this optimization allow generation of more compacted instructions.
run: clang -mcpu=cortex-m0 -target armv6m-none-eabi  icmp-shl-and.ll -O2 -S -o t.s 
@ %bb.0:                                @ %entry

  subs    r0, r0, #1
  lsls    r1, r0
  cmp     r1, #0
  blt     .LBB0_2

@ %bb.1:                                @ %entry

  mov     r2, r3

.LBB0_2:                                @ %entry

  mov     r0, r2
  bx      lr

Otherwise will generate more instructions with signmask shifting
@ %bb.0:                                @ %entry

  .save   {r4, lr}
  push    {r4, lr}
  subs    r0, r0, #1
  movs    r4, #1
  lsls    r4, r4, #31
  lsrs    r4, r0
  tst     r4, r1
  beq     .LBB0_2

@ %bb.1:                                @ %entry

  mov     r3, r2

.LBB0_2:                                @ %entry

  mov     r0, r3
  pop     {r4, pc}

ARM and thumb2 target allow flexible second operand, for this case test bit instruction with shift. This optimization does not affect performance of generated instructions.
Run: clang -mcpu=cortex-a53 -target armv8-none-musleabi  icmp-shl-and.ll -O2 -S -o t.s

With this optimization
@ %bb.0:                                @ %entry

  sub     r0, r0, #1
  lsl     r0, r1, r0
  cmp     r0, #0
  movge   r2, r3
  mov     r0, r2
  bx      lr

Without this optimization:
@ %bb.0:                                @ %entry

  sub     r12, r0, #1
  mov     r0, #-2147483648
  tst     r1, r0, lsr r12
  moveq   r2, r3
  mov     r0, r2
  bx      lr


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62818/new/

https://reviews.llvm.org/D62818