[PATCH] D62786: [X86] X86DAGToDAGISel::matchBitExtract(): pattern a: truncation awareness

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/Target/X86/X86ISelDAGToDAG.cpp:2997
+    if (V->getOpcode() == ISD::TRUNCATE && checkOneUse(V)) {
+      assert(V.getSimpleValueType() == MVT::i32);
+      V = V.getOperand(0);
----------------
assertion messages:
```
assert(V.getSimpleValueType() == MVT::i32 &&
           V.getOperand(0).getSimpleValueType() == MVT::i64 &&
           "Expected i64 -> i32 truncation");
```


================
Comment at: lib/Target/X86/X86ISelDAGToDAG.cpp:3149
+      X.getOperand(0).getOpcode() == ISD::SRL) {
+    assert(NVT == MVT::i32 && "Expected target valuetype to be i32");
+    X = X.getOperand(0);
----------------
Again, you can probably merge these asserts


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62786/new/

https://reviews.llvm.org/D62786