[llvm] r362188 - [X86] Add VP2INTERSECT instructions
Pengfei Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu May 30 19:50:42 PDT 2019
Author: pengfei
Date: Thu May 30 19:50:41 2019
New Revision: 362188
URL: http://llvm.org/viewvc/llvm-project?rev=362188&view=rev
Log:
[X86] Add VP2INTERSECT instructions
Support Intel AVX512 VP2INTERSECT instructions in llvm
Patch by Xiang Zhang (xiangzhangllvm)
Differential Revision: https://reviews.llvm.org/D62366
Added:
llvm/trunk/test/CodeGen/X86/avx512vlvp2intersect-intrinsics.ll
llvm/trunk/test/CodeGen/X86/avx512vp2intersect-intrinsics.ll
llvm/trunk/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
llvm/trunk/test/MC/Disassembler/X86/avx512-vp2intersect-32-att.txt
llvm/trunk/test/MC/Disassembler/X86/avx512-vp2intersect-64-att.txt
llvm/trunk/test/MC/Disassembler/X86/avx512_vp2intersect-32-intel.txt
llvm/trunk/test/MC/Disassembler/X86/avx512_vp2intersect-64-intel.txt
llvm/trunk/test/MC/Disassembler/X86/avx512vp2intersectvl-att.txt
llvm/trunk/test/MC/Disassembler/X86/avx512vp2intersectvl-intel.txt
llvm/trunk/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-att.txt
llvm/trunk/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-intel.txt
llvm/trunk/test/MC/X86/avx512vp2intersectvl-att.s
llvm/trunk/test/MC/X86/avx512vp2intersectvl-intel.s
llvm/trunk/test/MC/X86/x86-32-avx512_vp2intersect-intel.s
llvm/trunk/test/MC/X86/x86-32-avx512vp2intersect-att.s
llvm/trunk/test/MC/X86/x86-64-avx512_vp2intersect-intel.s
llvm/trunk/test/MC/X86/x86-64-avx512vp2intersect-att.s
llvm/trunk/test/MC/X86/x86-64-avx512vp2intersectvl-att.s
llvm/trunk/test/MC/X86/x86-64-avx512vp2intersectvl-intel.s
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsX86.td
llvm/trunk/include/llvm/Support/X86DisassemblerDecoderCommon.h
llvm/trunk/lib/Target/X86/AsmParser/X86Operand.h
llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h
llvm/trunk/lib/Target/X86/X86.td
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.td
llvm/trunk/lib/Target/X86/X86Subtarget.h
llvm/trunk/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Thu May 30 19:50:41 2019
@@ -4697,6 +4697,34 @@ let TargetPrefix = "x86" in {
[IntrNoMem, ImmArg<3>]>;
}
+// vp2intersect
+let TargetPrefix = "x86" in {
+ def int_x86_avx512_vp2intersect_q_512 :
+ Intrinsic<[llvm_v8i1_ty, llvm_v8i1_ty],
+ [llvm_v8i64_ty, llvm_v8i64_ty],
+ [IntrNoMem]>;
+ def int_x86_avx512_vp2intersect_q_256 :
+ Intrinsic<[llvm_v4i1_ty, llvm_v4i1_ty],
+ [llvm_v4i64_ty, llvm_v4i64_ty],
+ [IntrNoMem]>;
+ def int_x86_avx512_vp2intersect_q_128 :
+ Intrinsic<[llvm_v2i1_ty, llvm_v2i1_ty],
+ [llvm_v2i64_ty, llvm_v2i64_ty],
+ [IntrNoMem]>;
+ def int_x86_avx512_vp2intersect_d_512 :
+ Intrinsic<[llvm_v16i1_ty, llvm_v16i1_ty],
+ [llvm_v16i32_ty, llvm_v16i32_ty],
+ [IntrNoMem]>;
+ def int_x86_avx512_vp2intersect_d_256 :
+ Intrinsic<[llvm_v8i1_ty, llvm_v8i1_ty],
+ [llvm_v8i32_ty, llvm_v8i32_ty],
+ [IntrNoMem]>;
+ def int_x86_avx512_vp2intersect_d_128 :
+ Intrinsic<[llvm_v4i1_ty, llvm_v4i1_ty],
+ [llvm_v4i32_ty, llvm_v4i32_ty],
+ [IntrNoMem]>;
+}
+
// Misc.
let TargetPrefix = "x86" in {
// NOTE: These comparison intrinsics are not used by clang as long as the
Modified: llvm/trunk/include/llvm/Support/X86DisassemblerDecoderCommon.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/X86DisassemblerDecoderCommon.h?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/X86DisassemblerDecoderCommon.h (original)
+++ llvm/trunk/include/llvm/Support/X86DisassemblerDecoderCommon.h Thu May 30 19:50:41 2019
@@ -429,6 +429,7 @@ enum OperandEncoding {
ENUM_ENTRY(TYPE_YMM, "32-byte") \
ENUM_ENTRY(TYPE_ZMM, "64-byte") \
ENUM_ENTRY(TYPE_VK, "mask register") \
+ ENUM_ENTRY(TYPE_VK_PAIR, "mask register pair") \
ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
Modified: llvm/trunk/lib/Target/X86/AsmParser/X86Operand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86Operand.h?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86Operand.h (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86Operand.h Thu May 30 19:50:41 2019
@@ -451,6 +451,31 @@ struct X86Operand final : public MCParse
X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
}
+ bool isVK1Pair() const {
+ return Kind == Register &&
+ X86MCRegisterClasses[X86::VK1RegClassID].contains(getReg());
+ }
+
+ bool isVK2Pair() const {
+ return Kind == Register &&
+ X86MCRegisterClasses[X86::VK2RegClassID].contains(getReg());
+ }
+
+ bool isVK4Pair() const {
+ return Kind == Register &&
+ X86MCRegisterClasses[X86::VK4RegClassID].contains(getReg());
+ }
+
+ bool isVK8Pair() const {
+ return Kind == Register &&
+ X86MCRegisterClasses[X86::VK8RegClassID].contains(getReg());
+ }
+
+ bool isVK16Pair() const {
+ return Kind == Register &&
+ X86MCRegisterClasses[X86::VK16RegClassID].contains(getReg());
+ }
+
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
// Add as immediates when possible.
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
@@ -482,6 +507,30 @@ struct X86Operand final : public MCParse
addExpr(Inst, getImm());
}
+ void addMaskPairOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ unsigned Reg = getReg();
+ switch (Reg) {
+ case X86::K0:
+ case X86::K1:
+ Reg = X86::K0_K1;
+ break;
+ case X86::K2:
+ case X86::K3:
+ Reg = X86::K2_K3;
+ break;
+ case X86::K4:
+ case X86::K5:
+ Reg = X86::K4_K5;
+ break;
+ case X86::K6:
+ case X86::K7:
+ Reg = X86::K6_K7;
+ break;
+ }
+ Inst.addOperand(MCOperand::createReg(Reg));
+ }
+
void addMemOperands(MCInst &Inst, unsigned N) const {
assert((N == 5) && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Thu May 30 19:50:41 2019
@@ -694,6 +694,7 @@ static bool translateRM(MCInst &mcInst,
case TYPE_XMM:
case TYPE_YMM:
case TYPE_ZMM:
+ case TYPE_VK_PAIR:
case TYPE_VK:
case TYPE_DEBUGREG:
case TYPE_CONTROLREG:
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp Thu May 30 19:50:41 2019
@@ -1468,6 +1468,10 @@ static int readModRM(struct InternalInst
if (index > 7) \
*valid = 0; \
return prefix##_K0 + index; \
+ case TYPE_VK_PAIR: \
+ if (index > 7) \
+ *valid = 0; \
+ return prefix##_K0_K1 + (index / 2); \
case TYPE_MM64: \
return prefix##_MM0 + (index & 0x7); \
case TYPE_SEGMENTREG: \
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h Thu May 30 19:50:41 2019
@@ -324,6 +324,12 @@ namespace X86Disassembler {
ENTRY(K6) \
ENTRY(K7)
+#define REGS_MASK_PAIRS \
+ ENTRY(K0_K1) \
+ ENTRY(K2_K3) \
+ ENTRY(K4_K5) \
+ ENTRY(K6_K7)
+
#define REGS_SEGMENT \
ENTRY(ES) \
ENTRY(CS) \
@@ -393,6 +399,7 @@ namespace X86Disassembler {
REGS_YMM \
REGS_ZMM \
REGS_MASKS \
+ REGS_MASK_PAIRS \
REGS_SEGMENT \
REGS_DEBUG \
REGS_CONTROL \
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp Thu May 30 19:50:41 2019
@@ -335,3 +335,28 @@ void X86InstPrinterCommon::printInstFlag
else if (Flags & X86::IP_HAS_REPEAT)
O << "\trep\t";
}
+
+void X86InstPrinterCommon::printVKPair(const MCInst *MI, unsigned OpNo,
+ raw_ostream &OS) {
+ // In assembly listings, a pair is represented by one of its members, any
+ // of the two. Here, we pick k0, k2, k4, k6, but we could as well
+ // print K2_K3 as "k3". It would probably make a lot more sense, if
+ // the assembly would look something like:
+ // "vp2intersect %zmm5, %zmm7, {%k2, %k3}"
+ // but this can work too.
+ switch (MI->getOperand(OpNo).getReg()) {
+ case X86::K0_K1:
+ printRegName(OS, X86::K0);
+ return;
+ case X86::K2_K3:
+ printRegName(OS, X86::K2);
+ return;
+ case X86::K4_K5:
+ printRegName(OS, X86::K4);
+ return;
+ case X86::K6_K7:
+ printRegName(OS, X86::K6);
+ return;
+ }
+ llvm_unreachable("Unknown mask pair register name");
+}
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h Thu May 30 19:50:41 2019
@@ -33,6 +33,7 @@ public:
protected:
void printInstFlags(const MCInst *MI, raw_ostream &O);
void printOptionalSegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+ void printVKPair(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
};
} // end namespace llvm
Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Thu May 30 19:50:41 2019
@@ -173,6 +173,10 @@ def FeatureBF16 : SubtargetFeature<"a
def FeatureBITALG : SubtargetFeature<"avx512bitalg", "HasBITALG", "true",
"Enable AVX-512 Bit Algorithms",
[FeatureBWI]>;
+def FeatureVP2INTERSECT : SubtargetFeature<"avx512vp2intersect",
+ "HasVP2INTERSECT", "true",
+ "Enable AVX-512 vp2intersect",
+ [FeatureAVX512]>;
def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
"Enable packed carry-less multiplication instructions",
[FeatureSSE2]>;
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu May 30 19:50:41 2019
@@ -22944,6 +22944,28 @@ SDValue X86TargetLowering::LowerINTRINSI
}
return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
}
+
+ case Intrinsic::x86_avx512_vp2intersect_q_512:
+ case Intrinsic::x86_avx512_vp2intersect_q_256:
+ case Intrinsic::x86_avx512_vp2intersect_q_128:
+ case Intrinsic::x86_avx512_vp2intersect_d_512:
+ case Intrinsic::x86_avx512_vp2intersect_d_256:
+ case Intrinsic::x86_avx512_vp2intersect_d_128: {
+ MVT MaskVT = Op.getSimpleValueType();
+
+ SDVTList VTs = DAG.getVTList(MVT::Untyped, MVT::Other);
+ SDLoc DL(Op);
+
+ SDValue Operation =
+ DAG.getNode(X86ISD::VP2INTERSECT, DL, VTs,
+ Op->getOperand(1), Op->getOperand(2));
+
+ SDValue Result0 = DAG.getTargetExtractSubreg(X86::sub_mask_0, DL,
+ MaskVT, Operation);
+ SDValue Result1 = DAG.getTargetExtractSubreg(X86::sub_mask_1, DL,
+ MaskVT, Operation);
+ return DAG.getMergeValues({Result0, Result1}, DL);
+ }
}
}
@@ -28284,6 +28306,7 @@ const char *X86TargetLowering::getTarget
case X86ISD::TPAUSE: return "X86ISD::TPAUSE";
case X86ISD::ENQCMD: return "X86ISD:ENQCMD";
case X86ISD::ENQCMDS: return "X86ISD:ENQCMDS";
+ case X86ISD::VP2INTERSECT: return "X86ISD::VP2INTERSECT";
}
return nullptr;
}
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu May 30 19:50:41 2019
@@ -592,6 +592,9 @@ namespace llvm {
// Enqueue Stores Instructions
ENQCMD, ENQCMDS,
+ // For avx512-vp2intersect
+ VP2INTERSECT,
+
// Compare and swap.
LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
LCMPXCHG8_DAG,
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Thu May 30 19:50:41 2019
@@ -26,6 +26,10 @@ class X86VectorVTInfo<int numelts, Value
// Corresponding mask register class.
RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
+ // Corresponding mask register pair class.
+ RegisterOperand KRPC = !if (!gt(NumElts, 16), ?,
+ !cast<RegisterOperand>("VK" # NumElts # "Pair"));
+
// Corresponding write-mask register class.
RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
@@ -12556,6 +12560,59 @@ defm VP4DPWSSDSrm : AVX512_maskable_3src
Sched<[SchedWriteFMA.ZMM.Folded]>;
}
+let hasSideEffects = 0 in {
+ def MASKPAIR16STORE : PseudoI<(outs), (ins VK16PAIR:$src, anymem:$dst),
+ [(store VK16PAIR:$src, addr:$dst)]>;
+ def MASKPAIR16LOAD : PseudoI<(outs VK16PAIR:$dst), (ins anymem:$src),
+ [(set VK16PAIR:$dst, (load addr:$src))]>;
+}
+
+//===----------------------------------------------------------------------===//
+// VP2INTERSECT
+//===----------------------------------------------------------------------===//
+
+multiclass avx512_vp2intersect_modes<X86VectorVTInfo _> {
+ def rr : I<0x68, MRMSrcReg,
+ (outs _.KRPC:$dst),
+ (ins _.RC:$src1, _.RC:$src2),
+ !strconcat("vp2intersect", _.Suffix,
+ "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set _.KRPC:$dst, (X86vp2intersect
+ _.RC:$src1, (_.VT _.RC:$src2)))]>,
+ EVEX_4V, T8XD;
+
+ def rm : I<0x68, MRMSrcMem,
+ (outs _.KRPC:$dst),
+ (ins _.RC:$src1, _.MemOp:$src2),
+ !strconcat("vp2intersect", _.Suffix,
+ "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set _.KRPC:$dst, (X86vp2intersect
+ _.RC:$src1, (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
+ EVEX_4V, T8XD, EVEX_CD8<_.EltSize, CD8VF>;
+
+ def rmb : I<0x68, MRMSrcMem,
+ (outs _.KRPC:$dst),
+ (ins _.RC:$src1, _.ScalarMemOp:$src2),
+ !strconcat("vp2intersect", _.Suffix, "\t{${src2}", _.BroadcastStr,
+ ", $src1, $dst|$dst, $src1, ${src2}", _.BroadcastStr ,"}"),
+ [(set _.KRPC:$dst, (X86vp2intersect
+ _.RC:$src1, (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src2)))))]>,
+ EVEX_4V, T8XD, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
+}
+
+multiclass avx512_vp2intersect<AVX512VLVectorVTInfo _> {
+ let Predicates = [HasAVX512, HasVP2INTERSECT] in
+ defm Z : avx512_vp2intersect_modes<_.info512>, EVEX_V512;
+
+ let Predicates = [HasAVX512, HasVP2INTERSECT, HasVLX] in {
+ defm Z256 : avx512_vp2intersect_modes<_.info256>, EVEX_V256;
+ defm Z128 : avx512_vp2intersect_modes<_.info128>, EVEX_V128;
+ }
+}
+
+defm VP2INTERSECTD : avx512_vp2intersect<avx512vl_i32_info>;
+defm VP2INTERSECTQ : avx512_vp2intersect<avx512vl_i64_info>, VEX_W;
+
multiclass avx512_binop_all2<bits<8> opc, string OpcodeStr,
X86SchedWriteWidths sched,
AVX512VLVectorVTInfo _SrcVTInfo,
Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Thu May 30 19:50:41 2019
@@ -505,6 +505,10 @@ def X86FnmsubRnd : SDNode<"X86ISD::FN
def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound, [SDNPCommutative]>;
def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound, [SDNPCommutative]>;
+def X86vp2intersect : SDNode<"X86ISD::VP2INTERSECT",
+ SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
+ SDTCisVec<1>, SDTCisSameAs<1, 2>]>>;
+
def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>,
SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
def x86vpmadd52l : SDNode<"X86ISD::VPMADD52L", SDTIFma, [SDNPCommutative]>;
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu May 30 19:50:41 2019
@@ -2877,6 +2877,14 @@ static unsigned getLoadStoreRegOpcode(un
assert(STI.hasBWI() && "KMOVD requires BWI");
return load ? X86::KMOVDkm : X86::KMOVDmk;
}
+ // All of these mask pair classes have the same spill size, the same kind
+ // of kmov instructions can be used with all of them.
+ if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
+ X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
+ X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
+ X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
+ X86::VK16PAIRRegClass.hasSubClassEq(RC))
+ return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
llvm_unreachable("Unknown 4-byte regclass");
case 8:
if (X86::GR64RegClass.hasSubClassEq(RC))
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu May 30 19:50:41 2019
@@ -757,6 +757,33 @@ def lea64mem : Operand<i64> {
let ParserMatchClass = X86MemAsmOperand;
}
+let RenderMethod = "addMaskPairOperands" in {
+ def VK1PairAsmOperand : AsmOperandClass { let Name = "VK1Pair"; }
+ def VK2PairAsmOperand : AsmOperandClass { let Name = "VK2Pair"; }
+ def VK4PairAsmOperand : AsmOperandClass { let Name = "VK4Pair"; }
+ def VK8PairAsmOperand : AsmOperandClass { let Name = "VK8Pair"; }
+ def VK16PairAsmOperand : AsmOperandClass { let Name = "VK16Pair"; }
+}
+
+def VK1Pair : RegisterOperand<VK1PAIR, "printVKPair"> {
+ let ParserMatchClass = VK1PairAsmOperand;
+}
+
+def VK2Pair : RegisterOperand<VK2PAIR, "printVKPair"> {
+ let ParserMatchClass = VK2PairAsmOperand;
+}
+
+def VK4Pair : RegisterOperand<VK4PAIR, "printVKPair"> {
+ let ParserMatchClass = VK4PairAsmOperand;
+}
+
+def VK8Pair : RegisterOperand<VK8PAIR, "printVKPair"> {
+ let ParserMatchClass = VK8PairAsmOperand;
+}
+
+def VK16Pair : RegisterOperand<VK16PAIR, "printVKPair"> {
+ let ParserMatchClass = VK16PairAsmOperand;
+}
//===----------------------------------------------------------------------===//
// X86 Complex Pattern Definitions.
@@ -843,6 +870,7 @@ def NoVLX_Or_NoBWI : Predicate<"!Subtarg
def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">;
def PKU : Predicate<"Subtarget->hasPKU()">;
def HasVNNI : Predicate<"Subtarget->hasVNNI()">;
+def HasVP2INTERSECT : Predicate<"Subtarget->hasVP2INTERSECT()">;
def HasBF16 : Predicate<"Subtarget->hasBF16()">;
def HasBITALG : Predicate<"Subtarget->hasBITALG()">;
Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Thu May 30 19:50:41 2019
@@ -1680,6 +1680,77 @@ void X86AsmPrinter::EmitInstruction(cons
case X86::TLS_base_addr64:
return LowerTlsAddr(MCInstLowering, *MI);
+ // Loading/storing mask pairs requires two kmov operations. The second one of these
+ // needs a 2 byte displacement relative to the specified address (with 32 bit spill
+ // size). The pairs of 1bit masks up to 16 bit masks all use the same spill size,
+ // they all are stored using MASKPAIR16STORE, loaded using MASKPAIR16LOAD.
+ //
+ // The displacement value might wrap around in theory, thus the asserts in both
+ // cases.
+ case X86::MASKPAIR16LOAD: {
+ int64_t Disp = MI->getOperand(1 + X86::AddrDisp).getImm();
+ assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
+ const X86RegisterInfo *RI =
+ MF->getSubtarget<X86Subtarget>().getRegisterInfo();
+ unsigned Reg = MI->getOperand(0).getReg();
+ unsigned Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
+ unsigned Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);
+
+ // Load the first mask register
+ MCInstBuilder MIB = MCInstBuilder(X86::KMOVWkm);
+ MIB.addReg(Reg0);
+ for (int i = 0; i < X86::AddrNumOperands; ++i) {
+ auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i));
+ MIB.addOperand(Op.getValue());
+ }
+ EmitAndCountInstruction(MIB);
+
+ // Load the second mask register of the pair
+ MIB = MCInstBuilder(X86::KMOVWkm);
+ MIB.addReg(Reg1);
+ for (int i = 0; i < X86::AddrNumOperands; ++i) {
+ if (i == X86::AddrDisp) {
+ MIB.addImm(Disp + 2);
+ } else {
+ auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i));
+ MIB.addOperand(Op.getValue());
+ }
+ }
+ EmitAndCountInstruction(MIB);
+ return;
+ }
+
+ case X86::MASKPAIR16STORE: {
+ int64_t Disp = MI->getOperand(X86::AddrDisp).getImm();
+ assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
+ const X86RegisterInfo *RI =
+ MF->getSubtarget<X86Subtarget>().getRegisterInfo();
+ unsigned Reg = MI->getOperand(X86::AddrNumOperands).getReg();
+ unsigned Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
+ unsigned Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);
+
+ // Store the first mask register
+ MCInstBuilder MIB = MCInstBuilder(X86::KMOVWmk);
+ for (int i = 0; i < X86::AddrNumOperands; ++i)
+ MIB.addOperand(MCInstLowering.LowerMachineOperand(MI, MI->getOperand(i)).getValue());
+ MIB.addReg(Reg0);
+ EmitAndCountInstruction(MIB);
+
+ // Store the second mask register of the pair
+ MIB = MCInstBuilder(X86::KMOVWmk);
+ for (int i = 0; i < X86::AddrNumOperands; ++i) {
+ if (i == X86::AddrDisp) {
+ MIB.addImm(Disp + 2);
+ } else {
+ auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(0 + i));
+ MIB.addOperand(Op.getValue());
+ }
+ }
+ MIB.addReg(Reg1);
+ EmitAndCountInstruction(MIB);
+ return;
+ }
+
case X86::MOVPC32r: {
// This is a pseudo op for a two instruction sequence with a label, which
// looks like:
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Thu May 30 19:50:41 2019
@@ -28,6 +28,8 @@ let Namespace = "X86" in {
def sub_32bit : SubRegIndex<32>;
def sub_xmm : SubRegIndex<128>;
def sub_ymm : SubRegIndex<256>;
+ def sub_mask_0 : SubRegIndex<-1>;
+ def sub_mask_1 : SubRegIndex<-1, -1>;
}
//===----------------------------------------------------------------------===//
@@ -594,6 +596,16 @@ def VK16 : RegisterClass<"X86", [v16i
def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}
+// Mask register pairs
+def KPAIRS : RegisterTuples<[sub_mask_0, sub_mask_1],
+ [(add K0, K2, K4, K6), (add K1, K3, K5, K7)]>;
+
+def VK1PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
+def VK2PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
+def VK4PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
+def VK8PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
+def VK16PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
+
def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;}
def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;}
def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;}
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu May 30 19:50:41 2019
@@ -362,6 +362,9 @@ protected:
/// Processor has AVX-512 Bit Algorithms instructions
bool HasBITALG = false;
+ /// Processor has AVX-512 vp2intersect instructions
+ bool HasVP2INTERSECT = false;
+
/// Processor supports MPX - Memory Protection Extensions
bool HasMPX = false;
@@ -679,6 +682,7 @@ public:
bool hasPKU() const { return HasPKU; }
bool hasVNNI() const { return HasVNNI; }
bool hasBF16() const { return HasBF16; }
+ bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }
bool hasBITALG() const { return HasBITALG; }
bool hasMPX() const { return HasMPX; }
bool hasSHSTK() const { return HasSHSTK; }
Added: llvm/trunk/test/CodeGen/X86/avx512vlvp2intersect-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vlvp2intersect-intrinsics.ll?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vlvp2intersect-intrinsics.ll (added)
+++ llvm/trunk/test/CodeGen/X86/avx512vlvp2intersect-intrinsics.ll Thu May 30 19:50:41 2019
@@ -0,0 +1,593 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vp2intersect,+avx512vl --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vp2intersect,+avx512vl --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64
+
+define void @test_mm256_2intersect_epi32(<4 x i64> %a, <4 x i64> %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm256_2intersect_epi32:
+; X86: # %bb.0: # %entry
+; X86-NEXT: movl 4(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vp2intersectd %ymm1, %ymm0, %k0 # encoding: [0x62,0xf2,0x7f,0x28,0x68,0xc1]
+; X86-NEXT: kmovw %k1, %ecx # encoding: [0xc5,0xf8,0x93,0xc9]
+; X86-NEXT: kmovw %k0, %edx # encoding: [0xc5,0xf8,0x93,0xd0]
+; X86-NEXT: movb %dl, (%eax) # encoding: [0x88,0x10]
+; X86-NEXT: movl 8(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm256_2intersect_epi32:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vp2intersectd %ymm1, %ymm0, %k0 # encoding: [0x62,0xf2,0x7f,0x28,0x68,0xc1]
+; X64-NEXT: kmovw %k1, %eax # encoding: [0xc5,0xf8,0x93,0xc1]
+; X64-NEXT: kmovw %k0, %ecx # encoding: [0xc5,0xf8,0x93,0xc8]
+; X64-NEXT: movb %cl, (%rdi) # encoding: [0x88,0x0f]
+; X64-NEXT: movb %al, (%rsi) # encoding: [0x88,0x06]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = bitcast <4 x i64> %a to <8 x i32>
+ %1 = bitcast <4 x i64> %b to <8 x i32>
+ %2 = tail call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.d.256(<8 x i32> %0, <8 x i32> %1)
+ %3 = extractvalue { <8 x i1>, <8 x i1> } %2, 0
+ %4 = bitcast i8* %m0 to <8 x i1>*
+ store <8 x i1> %3, <8 x i1>* %4, align 8
+ %5 = extractvalue { <8 x i1>, <8 x i1> } %2, 1
+ %6 = bitcast i8* %m1 to <8 x i1>*
+ store <8 x i1> %5, <8 x i1>* %6, align 8
+ ret void
+}
+
+define void @test_mm256_2intersect_epi64(<4 x i64> %a, <4 x i64> %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm256_2intersect_epi64:
+; X86: # %bb.0: # %entry
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
+; X86-NEXT: vp2intersectq %ymm1, %ymm0, %k0 # encoding: [0x62,0xf2,0xff,0x28,0x68,0xc1]
+; X86-NEXT: kshiftlw $12, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0c]
+; X86-NEXT: kshiftrw $12, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0c]
+; X86-NEXT: kmovw %k2, %edx # encoding: [0xc5,0xf8,0x93,0xd2]
+; X86-NEXT: movb %dl, (%ecx) # encoding: [0x88,0x11]
+; X86-NEXT: kshiftlw $12, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0c]
+; X86-NEXT: kshiftrw $12, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0c]
+; X86-NEXT: kmovw %k0, %ecx # encoding: [0xc5,0xf8,0x93,0xc8]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm256_2intersect_epi64:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vp2intersectq %ymm1, %ymm0, %k0 # encoding: [0x62,0xf2,0xff,0x28,0x68,0xc1]
+; X64-NEXT: kshiftlw $12, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0c]
+; X64-NEXT: kshiftrw $12, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0c]
+; X64-NEXT: kmovw %k2, %eax # encoding: [0xc5,0xf8,0x93,0xc2]
+; X64-NEXT: movb %al, (%rdi) # encoding: [0x88,0x07]
+; X64-NEXT: kshiftlw $12, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0c]
+; X64-NEXT: kshiftrw $12, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0c]
+; X64-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
+; X64-NEXT: movb %al, (%rsi) # encoding: [0x88,0x06]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = tail call { <4 x i1>, <4 x i1> } @llvm.x86.avx512.vp2intersect.q.256(<4 x i64> %a, <4 x i64> %b)
+ %1 = extractvalue { <4 x i1>, <4 x i1> } %0, 0
+ %2 = shufflevector <4 x i1> %1, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %3 = bitcast <8 x i1> %2 to i8
+ store i8 %3, i8* %m0, align 1
+ %4 = extractvalue { <4 x i1>, <4 x i1> } %0, 1
+ %5 = shufflevector <4 x i1> %4, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %6 = bitcast <8 x i1> %5 to i8
+ store i8 %6, i8* %m1, align 1
+ ret void
+}
+
+define void @test_mm256_2intersect_epi32_p(<4 x i64>* nocapture readonly %a, <4 x i64>* nocapture readonly %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm256_2intersect_epi32_p:
+; X86: # %bb.0: # %entry
+; X86-NEXT: movl 12(%esp), %eax # encoding: [0x8b,0x44,0x24,0x0c]
+; X86-NEXT: movl 8(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x08]
+; X86-NEXT: movl 4(%esp), %edx # encoding: [0x8b,0x54,0x24,0x04]
+; X86-NEXT: vmovaps (%edx), %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0x02]
+; X86-NEXT: vp2intersectd (%ecx), %ymm0, %k0 # encoding: [0x62,0xf2,0x7f,0x28,0x68,0x01]
+; X86-NEXT: kmovw %k1, %ecx # encoding: [0xc5,0xf8,0x93,0xc9]
+; X86-NEXT: kmovw %k0, %edx # encoding: [0xc5,0xf8,0x93,0xd0]
+; X86-NEXT: movb %dl, (%eax) # encoding: [0x88,0x10]
+; X86-NEXT: movl 16(%esp), %eax # encoding: [0x8b,0x44,0x24,0x10]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm256_2intersect_epi32_p:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vmovaps (%rdi), %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0x07]
+; X64-NEXT: vp2intersectd (%rsi), %ymm0, %k0 # encoding: [0x62,0xf2,0x7f,0x28,0x68,0x06]
+; X64-NEXT: kmovw %k1, %eax # encoding: [0xc5,0xf8,0x93,0xc1]
+; X64-NEXT: kmovw %k0, %esi # encoding: [0xc5,0xf8,0x93,0xf0]
+; X64-NEXT: movb %sil, (%rdx) # encoding: [0x40,0x88,0x32]
+; X64-NEXT: movb %al, (%rcx) # encoding: [0x88,0x01]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = bitcast <4 x i64>* %a to <8 x i32>*
+ %1 = load <8 x i32>, <8 x i32>* %0, align 32
+ %2 = bitcast <4 x i64>* %b to <8 x i32>*
+ %3 = load <8 x i32>, <8 x i32>* %2, align 32
+ %4 = tail call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.d.256(<8 x i32> %1, <8 x i32> %3)
+ %5 = extractvalue { <8 x i1>, <8 x i1> } %4, 0
+ %6 = bitcast i8* %m0 to <8 x i1>*
+ store <8 x i1> %5, <8 x i1>* %6, align 8
+ %7 = extractvalue { <8 x i1>, <8 x i1> } %4, 1
+ %8 = bitcast i8* %m1 to <8 x i1>*
+ store <8 x i1> %7, <8 x i1>* %8, align 8
+ ret void
+}
+
+define void @test_mm256_2intersect_epi64_p(<4 x i64>* nocapture readonly %a, <4 x i64>* nocapture readonly %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm256_2intersect_epi64_p:
+; X86: .cfi_startproc
+; X86-NEXT: # %bb.0: # %entry
+; X86-NEXT: pushl %esi # encoding: [0x56]
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %esi, -8
+; X86-NEXT: movl 20(%esp), %eax # encoding: [0x8b,0x44,0x24,0x14]
+; X86-NEXT: movl 16(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x10]
+; X86-NEXT: movl 12(%esp), %edx # encoding: [0x8b,0x54,0x24,0x0c]
+; X86-NEXT: movl 8(%esp), %esi # encoding: [0x8b,0x74,0x24,0x08]
+; X86-NEXT: vmovaps (%esi), %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0x06]
+; X86-NEXT: vp2intersectq (%edx), %ymm0, %k0 # encoding: [0x62,0xf2,0xff,0x28,0x68,0x02]
+; X86-NEXT: kshiftlw $12, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0c]
+; X86-NEXT: kshiftrw $12, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0c]
+; X86-NEXT: kmovw %k2, %edx # encoding: [0xc5,0xf8,0x93,0xd2]
+; X86-NEXT: movb %dl, (%ecx) # encoding: [0x88,0x11]
+; X86-NEXT: kshiftlw $12, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0c]
+; X86-NEXT: kshiftrw $12, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0c]
+; X86-NEXT: kmovw %k0, %ecx # encoding: [0xc5,0xf8,0x93,0xc8]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: popl %esi # encoding: [0x5e]
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm256_2intersect_epi64_p:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vmovaps (%rdi), %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0x07]
+; X64-NEXT: vp2intersectq (%rsi), %ymm0, %k0 # encoding: [0x62,0xf2,0xff,0x28,0x68,0x06]
+; X64-NEXT: kshiftlw $12, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0c]
+; X64-NEXT: kshiftrw $12, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0c]
+; X64-NEXT: kmovw %k2, %eax # encoding: [0xc5,0xf8,0x93,0xc2]
+; X64-NEXT: movb %al, (%rdx) # encoding: [0x88,0x02]
+; X64-NEXT: kshiftlw $12, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0c]
+; X64-NEXT: kshiftrw $12, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0c]
+; X64-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
+; X64-NEXT: movb %al, (%rcx) # encoding: [0x88,0x01]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = load <4 x i64>, <4 x i64>* %a, align 32
+ %1 = load <4 x i64>, <4 x i64>* %b, align 32
+ %2 = tail call { <4 x i1>, <4 x i1> } @llvm.x86.avx512.vp2intersect.q.256(<4 x i64> %0, <4 x i64> %1)
+ %3 = extractvalue { <4 x i1>, <4 x i1> } %2, 0
+ %4 = shufflevector <4 x i1> %3, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %5 = bitcast <8 x i1> %4 to i8
+ store i8 %5, i8* %m0, align 1
+ %6 = extractvalue { <4 x i1>, <4 x i1> } %2, 1
+ %7 = shufflevector <4 x i1> %6, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %8 = bitcast <8 x i1> %7 to i8
+ store i8 %8, i8* %m1, align 1
+ ret void
+}
+
+define void @test_mm256_2intersect_epi32_b(i32* nocapture readonly %a, i32* nocapture readonly %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm256_2intersect_epi32_b:
+; X86: .cfi_startproc
+; X86-NEXT: # %bb.0: # %entry
+; X86-NEXT: movl 12(%esp), %eax # encoding: [0x8b,0x44,0x24,0x0c]
+; X86-NEXT: movl 8(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x08]
+; X86-NEXT: movl 4(%esp), %edx # encoding: [0x8b,0x54,0x24,0x04]
+; X86-NEXT: vbroadcastss (%edx), %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x18,0x02]
+; X86-NEXT: vp2intersectd (%ecx){1to8}, %ymm0, %k0 # encoding: [0x62,0xf2,0x7f,0x38,0x68,0x01]
+; X86-NEXT: kmovw %k1, %ecx # encoding: [0xc5,0xf8,0x93,0xc9]
+; X86-NEXT: kmovw %k0, %edx # encoding: [0xc5,0xf8,0x93,0xd0]
+; X86-NEXT: movb %dl, (%eax) # encoding: [0x88,0x10]
+; X86-NEXT: movl 16(%esp), %eax # encoding: [0x8b,0x44,0x24,0x10]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm256_2intersect_epi32_b:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vbroadcastss (%rdi), %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x18,0x07]
+; X64-NEXT: vp2intersectd (%rsi){1to8}, %ymm0, %k0 # encoding: [0x62,0xf2,0x7f,0x38,0x68,0x06]
+; X64-NEXT: kmovw %k1, %eax # encoding: [0xc5,0xf8,0x93,0xc1]
+; X64-NEXT: kmovw %k0, %esi # encoding: [0xc5,0xf8,0x93,0xf0]
+; X64-NEXT: movb %sil, (%rdx) # encoding: [0x40,0x88,0x32]
+; X64-NEXT: movb %al, (%rcx) # encoding: [0x88,0x01]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = load i32, i32* %a, align 4
+ %vecinit.i.i = insertelement <8 x i32> undef, i32 %0, i32 0
+ %vecinit7.i.i = shufflevector <8 x i32> %vecinit.i.i, <8 x i32> undef, <8 x i32> zeroinitializer
+ %1 = load i32, i32* %b, align 4
+ %vecinit.i.i2 = insertelement <8 x i32> undef, i32 %1, i32 0
+ %vecinit7.i.i3 = shufflevector <8 x i32> %vecinit.i.i2, <8 x i32> undef, <8 x i32> zeroinitializer
+ %2 = tail call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.d.256(<8 x i32> %vecinit7.i.i, <8 x i32> %vecinit7.i.i3)
+ %3 = extractvalue { <8 x i1>, <8 x i1> } %2, 0
+ %4 = bitcast i8* %m0 to <8 x i1>*
+ store <8 x i1> %3, <8 x i1>* %4, align 8
+ %5 = extractvalue { <8 x i1>, <8 x i1> } %2, 1
+ %6 = bitcast i8* %m1 to <8 x i1>*
+ store <8 x i1> %5, <8 x i1>* %6, align 8
+ ret void
+}
+
+define void @test_mm256_2intersect_epi64_b(i64* nocapture readonly %a, i64* nocapture readonly %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm256_2intersect_epi64_b:
+; X86: .cfi_startproc
+; X86-NEXT: # %bb.0: # %entry
+; X86-NEXT: pushl %esi # encoding: [0x56]
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %esi, -8
+; X86-NEXT: movl 20(%esp), %eax # encoding: [0x8b,0x44,0x24,0x14]
+; X86-NEXT: movl 16(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x10]
+; X86-NEXT: movl 12(%esp), %edx # encoding: [0x8b,0x54,0x24,0x0c]
+; X86-NEXT: movl 8(%esp), %esi # encoding: [0x8b,0x74,0x24,0x08]
+; X86-NEXT: vbroadcastsd (%esi), %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x19,0x06]
+; X86-NEXT: vbroadcastsd (%edx), %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x19,0x0a]
+; X86-NEXT: vp2intersectq %ymm1, %ymm0, %k0 # encoding: [0x62,0xf2,0xff,0x28,0x68,0xc1]
+; X86-NEXT: kshiftlw $12, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0c]
+; X86-NEXT: kshiftrw $12, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0c]
+; X86-NEXT: kmovw %k2, %edx # encoding: [0xc5,0xf8,0x93,0xd2]
+; X86-NEXT: movb %dl, (%ecx) # encoding: [0x88,0x11]
+; X86-NEXT: kshiftlw $12, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0c]
+; X86-NEXT: kshiftrw $12, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0c]
+; X86-NEXT: kmovw %k0, %ecx # encoding: [0xc5,0xf8,0x93,0xc8]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: popl %esi # encoding: [0x5e]
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm256_2intersect_epi64_b:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vbroadcastsd (%rdi), %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x19,0x07]
+; X64-NEXT: vp2intersectq (%rsi){1to4}, %ymm0, %k0 # encoding: [0x62,0xf2,0xff,0x38,0x68,0x06]
+; X64-NEXT: kshiftlw $12, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0c]
+; X64-NEXT: kshiftrw $12, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0c]
+; X64-NEXT: kmovw %k2, %eax # encoding: [0xc5,0xf8,0x93,0xc2]
+; X64-NEXT: movb %al, (%rdx) # encoding: [0x88,0x02]
+; X64-NEXT: kshiftlw $12, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0c]
+; X64-NEXT: kshiftrw $12, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0c]
+; X64-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
+; X64-NEXT: movb %al, (%rcx) # encoding: [0x88,0x01]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = load i64, i64* %a, align 8
+ %vecinit.i.i = insertelement <4 x i64> undef, i64 %0, i32 0
+ %vecinit3.i.i = shufflevector <4 x i64> %vecinit.i.i, <4 x i64> undef, <4 x i32> zeroinitializer
+ %1 = load i64, i64* %b, align 8
+ %vecinit.i.i2 = insertelement <4 x i64> undef, i64 %1, i32 0
+ %vecinit3.i.i3 = shufflevector <4 x i64> %vecinit.i.i2, <4 x i64> undef, <4 x i32> zeroinitializer
+ %2 = tail call { <4 x i1>, <4 x i1> } @llvm.x86.avx512.vp2intersect.q.256(<4 x i64> %vecinit3.i.i, <4 x i64> %vecinit3.i.i3)
+ %3 = extractvalue { <4 x i1>, <4 x i1> } %2, 0
+ %4 = shufflevector <4 x i1> %3, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %5 = bitcast <8 x i1> %4 to i8
+ store i8 %5, i8* %m0, align 1
+ %6 = extractvalue { <4 x i1>, <4 x i1> } %2, 1
+ %7 = shufflevector <4 x i1> %6, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %8 = bitcast <8 x i1> %7 to i8
+ store i8 %8, i8* %m1, align 1
+ ret void
+}
+
+define void @test_mm_2intersect_epi32(<2 x i64> %a, <2 x i64> %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm_2intersect_epi32:
+; X86: .cfi_startproc
+; X86-NEXT: # %bb.0: # %entry
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
+; X86-NEXT: vp2intersectd %xmm1, %xmm0, %k0 # encoding: [0x62,0xf2,0x7f,0x08,0x68,0xc1]
+; X86-NEXT: kshiftlw $12, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0c]
+; X86-NEXT: kshiftrw $12, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0c]
+; X86-NEXT: kmovw %k2, %edx # encoding: [0xc5,0xf8,0x93,0xd2]
+; X86-NEXT: movb %dl, (%ecx) # encoding: [0x88,0x11]
+; X86-NEXT: kshiftlw $12, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0c]
+; X86-NEXT: kshiftrw $12, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0c]
+; X86-NEXT: kmovw %k0, %ecx # encoding: [0xc5,0xf8,0x93,0xc8]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm_2intersect_epi32:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vp2intersectd %xmm1, %xmm0, %k0 # encoding: [0x62,0xf2,0x7f,0x08,0x68,0xc1]
+; X64-NEXT: kshiftlw $12, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0c]
+; X64-NEXT: kshiftrw $12, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0c]
+; X64-NEXT: kmovw %k2, %eax # encoding: [0xc5,0xf8,0x93,0xc2]
+; X64-NEXT: movb %al, (%rdi) # encoding: [0x88,0x07]
+; X64-NEXT: kshiftlw $12, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0c]
+; X64-NEXT: kshiftrw $12, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0c]
+; X64-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
+; X64-NEXT: movb %al, (%rsi) # encoding: [0x88,0x06]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = bitcast <2 x i64> %a to <4 x i32>
+ %1 = bitcast <2 x i64> %b to <4 x i32>
+ %2 = tail call { <4 x i1>, <4 x i1> } @llvm.x86.avx512.vp2intersect.d.128(<4 x i32> %0, <4 x i32> %1)
+ %3 = extractvalue { <4 x i1>, <4 x i1> } %2, 0
+ %4 = shufflevector <4 x i1> %3, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %5 = bitcast <8 x i1> %4 to i8
+ store i8 %5, i8* %m0, align 1
+ %6 = extractvalue { <4 x i1>, <4 x i1> } %2, 1
+ %7 = shufflevector <4 x i1> %6, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %8 = bitcast <8 x i1> %7 to i8
+ store i8 %8, i8* %m1, align 1
+ ret void
+}
+
+define void @test_mm_2intersect_epi64(<2 x i64> %a, <2 x i64> %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm_2intersect_epi64:
+; X86: # %bb.0: # %entry
+; X86-NEXT: movl 8(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
+; X86-NEXT: movl 4(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
+; X86-NEXT: vp2intersectq %xmm1, %xmm0, %k0 # encoding: [0x62,0xf2,0xff,0x08,0x68,0xc1]
+; X86-NEXT: kshiftlw $14, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0e]
+; X86-NEXT: kshiftrw $14, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0e]
+; X86-NEXT: kmovw %k2, %edx # encoding: [0xc5,0xf8,0x93,0xd2]
+; X86-NEXT: movb %dl, (%ecx) # encoding: [0x88,0x11]
+; X86-NEXT: kshiftlw $14, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0e]
+; X86-NEXT: kshiftrw $14, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0e]
+; X86-NEXT: kmovw %k0, %ecx # encoding: [0xc5,0xf8,0x93,0xc8]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm_2intersect_epi64:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vp2intersectq %xmm1, %xmm0, %k0 # encoding: [0x62,0xf2,0xff,0x08,0x68,0xc1]
+; X64-NEXT: kshiftlw $14, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0e]
+; X64-NEXT: kshiftrw $14, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0e]
+; X64-NEXT: kmovw %k2, %eax # encoding: [0xc5,0xf8,0x93,0xc2]
+; X64-NEXT: movb %al, (%rdi) # encoding: [0x88,0x07]
+; X64-NEXT: kshiftlw $14, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0e]
+; X64-NEXT: kshiftrw $14, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0e]
+; X64-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
+; X64-NEXT: movb %al, (%rsi) # encoding: [0x88,0x06]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = tail call { <2 x i1>, <2 x i1> } @llvm.x86.avx512.vp2intersect.q.128(<2 x i64> %a, <2 x i64> %b)
+ %1 = extractvalue { <2 x i1>, <2 x i1> } %0, 0
+ %2 = shufflevector <2 x i1> %1, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
+ %3 = bitcast <8 x i1> %2 to i8
+ store i8 %3, i8* %m0, align 1
+ %4 = extractvalue { <2 x i1>, <2 x i1> } %0, 1
+ %5 = shufflevector <2 x i1> %4, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
+ %6 = bitcast <8 x i1> %5 to i8
+ store i8 %6, i8* %m1, align 1
+ ret void
+}
+
+define void @test_mm_2intersect_epi32_p(<2 x i64>* nocapture readonly %a, <2 x i64>* nocapture readonly %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm_2intersect_epi32_p:
+; X86: # %bb.0: # %entry
+; X86-NEXT: pushl %esi # encoding: [0x56]
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %esi, -8
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x14]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x10]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx # encoding: [0x8b,0x54,0x24,0x0c]
+; X86-NEXT: movl 8(%esp), %esi # encoding: [0x8b,0x74,0x24,0x08]
+; X86-NEXT: vmovaps (%esi), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0x06]
+; X86-NEXT: vp2intersectd (%edx), %xmm0, %k0 # encoding: [0x62,0xf2,0x7f,0x08,0x68,0x02]
+; X86-NEXT: kshiftlw $12, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0c]
+; X86-NEXT: kshiftrw $12, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0c]
+; X86-NEXT: kmovw %k2, %edx # encoding: [0xc5,0xf8,0x93,0xd2]
+; X86-NEXT: movb %dl, (%ecx) # encoding: [0x88,0x11]
+; X86-NEXT: kshiftlw $12, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0c]
+; X86-NEXT: kshiftrw $12, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0c]
+; X86-NEXT: kmovw %k0, %ecx # encoding: [0xc5,0xf8,0x93,0xc8]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: popl %esi # encoding: [0x5e]
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm_2intersect_epi32_p:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vmovaps (%rdi), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0x07]
+; X64-NEXT: vp2intersectd (%rsi), %xmm0, %k0 # encoding: [0x62,0xf2,0x7f,0x08,0x68,0x06]
+; X64-NEXT: kshiftlw $12, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0c]
+; X64-NEXT: kshiftrw $12, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0c]
+; X64-NEXT: kmovw %k2, %eax # encoding: [0xc5,0xf8,0x93,0xc2]
+; X64-NEXT: movb %al, (%rdx) # encoding: [0x88,0x02]
+; X64-NEXT: kshiftlw $12, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0c]
+; X64-NEXT: kshiftrw $12, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0c]
+; X64-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
+; X64-NEXT: movb %al, (%rcx) # encoding: [0x88,0x01]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = bitcast <2 x i64>* %a to <4 x i32>*
+ %1 = load <4 x i32>, <4 x i32>* %0, align 16
+ %2 = bitcast <2 x i64>* %b to <4 x i32>*
+ %3 = load <4 x i32>, <4 x i32>* %2, align 16
+ %4 = tail call { <4 x i1>, <4 x i1> } @llvm.x86.avx512.vp2intersect.d.128(<4 x i32> %1, <4 x i32> %3)
+ %5 = extractvalue { <4 x i1>, <4 x i1> } %4, 0
+ %6 = shufflevector <4 x i1> %5, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %7 = bitcast <8 x i1> %6 to i8
+ store i8 %7, i8* %m0, align 1
+ %8 = extractvalue { <4 x i1>, <4 x i1> } %4, 1
+ %9 = shufflevector <4 x i1> %8, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %10 = bitcast <8 x i1> %9 to i8
+ store i8 %10, i8* %m1, align 1
+ ret void
+}
+
+define void @test_mm_2intersect_epi64_p(<2 x i64>* nocapture readonly %a, <2 x i64>* nocapture readonly %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm_2intersect_epi64_p:
+; X86: # %bb.0: # %entry
+; X86-NEXT: pushl %esi # encoding: [0x56]
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %esi, -8
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x14]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x10]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx # encoding: [0x8b,0x54,0x24,0x0c]
+; X86-NEXT: movl 8(%esp), %esi # encoding: [0x8b,0x74,0x24,0x08]
+; X86-NEXT: vmovaps (%esi), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0x06]
+; X86-NEXT: vp2intersectq (%edx), %xmm0, %k0 # encoding: [0x62,0xf2,0xff,0x08,0x68,0x02]
+; X86-NEXT: kshiftlw $14, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0e]
+; X86-NEXT: kshiftrw $14, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0e]
+; X86-NEXT: kmovw %k2, %edx # encoding: [0xc5,0xf8,0x93,0xd2]
+; X86-NEXT: movb %dl, (%ecx) # encoding: [0x88,0x11]
+; X86-NEXT: kshiftlw $14, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0e]
+; X86-NEXT: kshiftrw $14, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0e]
+; X86-NEXT: kmovw %k0, %ecx # encoding: [0xc5,0xf8,0x93,0xc8]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: popl %esi # encoding: [0x5e]
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm_2intersect_epi64_p:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vmovaps (%rdi), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0x07]
+; X64-NEXT: vp2intersectq (%rsi), %xmm0, %k0 # encoding: [0x62,0xf2,0xff,0x08,0x68,0x06]
+; X64-NEXT: kshiftlw $14, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0e]
+; X64-NEXT: kshiftrw $14, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0e]
+; X64-NEXT: kmovw %k2, %eax # encoding: [0xc5,0xf8,0x93,0xc2]
+; X64-NEXT: movb %al, (%rdx) # encoding: [0x88,0x02]
+; X64-NEXT: kshiftlw $14, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0e]
+; X64-NEXT: kshiftrw $14, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0e]
+; X64-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
+; X64-NEXT: movb %al, (%rcx) # encoding: [0x88,0x01]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = load <2 x i64>, <2 x i64>* %a, align 16
+ %1 = load <2 x i64>, <2 x i64>* %b, align 16
+ %2 = tail call { <2 x i1>, <2 x i1> } @llvm.x86.avx512.vp2intersect.q.128(<2 x i64> %0, <2 x i64> %1)
+ %3 = extractvalue { <2 x i1>, <2 x i1> } %2, 0
+ %4 = shufflevector <2 x i1> %3, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
+ %5 = bitcast <8 x i1> %4 to i8
+ store i8 %5, i8* %m0, align 1
+ %6 = extractvalue { <2 x i1>, <2 x i1> } %2, 1
+ %7 = shufflevector <2 x i1> %6, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
+ %8 = bitcast <8 x i1> %7 to i8
+ store i8 %8, i8* %m1, align 1
+ ret void
+}
+
+define void @test_mm_2intersect_epi32_b(i32* nocapture readonly %a, i32* nocapture readonly %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm_2intersect_epi32_b:
+; X86: # %bb.0: # %entry
+; X86-NEXT: pushl %esi # encoding: [0x56]
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %esi, -8
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x14]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x10]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx # encoding: [0x8b,0x54,0x24,0x0c]
+; X86-NEXT: movl 8(%esp), %esi # encoding: [0x8b,0x74,0x24,0x08]
+; X86-NEXT: vbroadcastss (%esi), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x18,0x06]
+; X86-NEXT: vp2intersectd (%edx){1to4}, %xmm0, %k0 # encoding: [0x62,0xf2,0x7f,0x18,0x68,0x02]
+; X86-NEXT: kshiftlw $12, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0c]
+; X86-NEXT: kshiftrw $12, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0c]
+; X86-NEXT: kmovw %k2, %edx # encoding: [0xc5,0xf8,0x93,0xd2]
+; X86-NEXT: movb %dl, (%ecx) # encoding: [0x88,0x11]
+; X86-NEXT: kshiftlw $12, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0c]
+; X86-NEXT: kshiftrw $12, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0c]
+; X86-NEXT: kmovw %k0, %ecx # encoding: [0xc5,0xf8,0x93,0xc8]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: popl %esi # encoding: [0x5e]
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm_2intersect_epi32_b:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vbroadcastss (%rdi), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x18,0x07]
+; X64-NEXT: vp2intersectd (%rsi){1to4}, %xmm0, %k0 # encoding: [0x62,0xf2,0x7f,0x18,0x68,0x06]
+; X64-NEXT: kshiftlw $12, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0c]
+; X64-NEXT: kshiftrw $12, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0c]
+; X64-NEXT: kmovw %k2, %eax # encoding: [0xc5,0xf8,0x93,0xc2]
+; X64-NEXT: movb %al, (%rdx) # encoding: [0x88,0x02]
+; X64-NEXT: kshiftlw $12, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0c]
+; X64-NEXT: kshiftrw $12, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0c]
+; X64-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
+; X64-NEXT: movb %al, (%rcx) # encoding: [0x88,0x01]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = load i32, i32* %a, align 4
+ %vecinit.i.i = insertelement <4 x i32> undef, i32 %0, i32 0
+ %vecinit3.i.i = shufflevector <4 x i32> %vecinit.i.i, <4 x i32> undef, <4 x i32> zeroinitializer
+ %1 = load i32, i32* %b, align 4
+ %vecinit.i.i2 = insertelement <4 x i32> undef, i32 %1, i32 0
+ %vecinit3.i.i3 = shufflevector <4 x i32> %vecinit.i.i2, <4 x i32> undef, <4 x i32> zeroinitializer
+ %2 = tail call { <4 x i1>, <4 x i1> } @llvm.x86.avx512.vp2intersect.d.128(<4 x i32> %vecinit3.i.i, <4 x i32> %vecinit3.i.i3)
+ %3 = extractvalue { <4 x i1>, <4 x i1> } %2, 0
+ %4 = shufflevector <4 x i1> %3, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %5 = bitcast <8 x i1> %4 to i8
+ store i8 %5, i8* %m0, align 1
+ %6 = extractvalue { <4 x i1>, <4 x i1> } %2, 1
+ %7 = shufflevector <4 x i1> %6, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %8 = bitcast <8 x i1> %7 to i8
+ store i8 %8, i8* %m1, align 1
+ ret void
+}
+
+define void @test_mm_2intersect_epi64_b(i64* nocapture readonly %a, i64* nocapture readonly %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm_2intersect_epi64_b:
+; X86: # %bb.0: # %entry
+; X86-NEXT: pushl %esi # encoding: [0x56]
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %esi, -8
+; X86-NEXT: movl 20(%esp), %eax # encoding: [0x8b,0x44,0x24,0x14]
+; X86-NEXT: movl 16(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x10]
+; X86-NEXT: movl 12(%esp), %edx # encoding: [0x8b,0x54,0x24,0x0c]
+; X86-NEXT: movl 8(%esp), %esi # encoding: [0x8b,0x74,0x24,0x08]
+; X86-NEXT: vmovddup (%esi), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x12,0x06]
+; X86-NEXT: # xmm0 = mem[0,0]
+; X86-NEXT: vmovddup (%edx), %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x12,0x0a]
+; X86-NEXT: # xmm1 = mem[0,0]
+; X86-NEXT: vp2intersectq %xmm1, %xmm0, %k0 # encoding: [0x62,0xf2,0xff,0x08,0x68,0xc1]
+; X86-NEXT: kshiftlw $14, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0e]
+; X86-NEXT: kshiftrw $14, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0e]
+; X86-NEXT: kmovw %k2, %edx # encoding: [0xc5,0xf8,0x93,0xd2]
+; X86-NEXT: movb %dl, (%ecx) # encoding: [0x88,0x11]
+; X86-NEXT: kshiftlw $14, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0e]
+; X86-NEXT: kshiftrw $14, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0e]
+; X86-NEXT: kmovw %k0, %ecx # encoding: [0xc5,0xf8,0x93,0xc8]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: popl %esi # encoding: [0x5e]
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm_2intersect_epi64_b:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vmovddup (%rdi), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x12,0x07]
+; X64-NEXT: # xmm0 = mem[0,0]
+; X64-NEXT: vp2intersectq (%rsi){1to2}, %xmm0, %k0 # encoding: [0x62,0xf2,0xff,0x18,0x68,0x06]
+; X64-NEXT: kshiftlw $14, %k0, %k2 # encoding: [0xc4,0xe3,0xf9,0x32,0xd0,0x0e]
+; X64-NEXT: kshiftrw $14, %k2, %k2 # encoding: [0xc4,0xe3,0xf9,0x30,0xd2,0x0e]
+; X64-NEXT: kmovw %k2, %eax # encoding: [0xc5,0xf8,0x93,0xc2]
+; X64-NEXT: movb %al, (%rdx) # encoding: [0x88,0x02]
+; X64-NEXT: kshiftlw $14, %k1, %k0 # encoding: [0xc4,0xe3,0xf9,0x32,0xc1,0x0e]
+; X64-NEXT: kshiftrw $14, %k0, %k0 # encoding: [0xc4,0xe3,0xf9,0x30,0xc0,0x0e]
+; X64-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
+; X64-NEXT: movb %al, (%rcx) # encoding: [0x88,0x01]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = load i64, i64* %a, align 8
+ %vecinit.i.i = insertelement <2 x i64> undef, i64 %0, i32 0
+ %vecinit1.i.i = shufflevector <2 x i64> %vecinit.i.i, <2 x i64> undef, <2 x i32> zeroinitializer
+ %1 = load i64, i64* %b, align 8
+ %vecinit.i.i2 = insertelement <2 x i64> undef, i64 %1, i32 0
+ %vecinit1.i.i3 = shufflevector <2 x i64> %vecinit.i.i2, <2 x i64> undef, <2 x i32> zeroinitializer
+ %2 = tail call { <2 x i1>, <2 x i1> } @llvm.x86.avx512.vp2intersect.q.128(<2 x i64> %vecinit1.i.i, <2 x i64> %vecinit1.i.i3)
+ %3 = extractvalue { <2 x i1>, <2 x i1> } %2, 0
+ %4 = shufflevector <2 x i1> %3, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
+ %5 = bitcast <8 x i1> %4 to i8
+ store i8 %5, i8* %m0, align 1
+ %6 = extractvalue { <2 x i1>, <2 x i1> } %2, 1
+ %7 = shufflevector <2 x i1> %6, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
+ %8 = bitcast <8 x i1> %7 to i8
+ store i8 %8, i8* %m1, align 1
+ ret void
+}
+
+declare { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.d.256(<8 x i32>, <8 x i32>)
+declare { <4 x i1>, <4 x i1> } @llvm.x86.avx512.vp2intersect.q.256(<4 x i64>, <4 x i64>)
+declare { <4 x i1>, <4 x i1> } @llvm.x86.avx512.vp2intersect.d.128(<4 x i32>, <4 x i32>)
+declare { <2 x i1>, <2 x i1> } @llvm.x86.avx512.vp2intersect.q.128(<2 x i64>, <2 x i64>)
Added: llvm/trunk/test/CodeGen/X86/avx512vp2intersect-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vp2intersect-intrinsics.ll?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vp2intersect-intrinsics.ll (added)
+++ llvm/trunk/test/CodeGen/X86/avx512vp2intersect-intrinsics.ll Thu May 30 19:50:41 2019
@@ -0,0 +1,240 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vp2intersect --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vp2intersect --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64
+
+define void @test_mm512_2intersect_epi32(<8 x i64> %a, <8 x i64> %b, i16* nocapture %m0, i16* nocapture %m1) {
+; X86-LABEL: test_mm512_2intersect_epi32:
+; X86: # %bb.0: # %entry
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
+; X86-NEXT: vp2intersectd %zmm1, %zmm0, %k0 # encoding: [0x62,0xf2,0x7f,0x48,0x68,0xc1]
+; X86-NEXT: kmovw %k0, (%ecx) # encoding: [0xc5,0xf8,0x91,0x01]
+; X86-NEXT: kmovw %k1, (%eax) # encoding: [0xc5,0xf8,0x91,0x08]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm512_2intersect_epi32:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vp2intersectd %zmm1, %zmm0, %k0 # encoding: [0x62,0xf2,0x7f,0x48,0x68,0xc1]
+; X64-NEXT: kmovw %k0, (%rdi) # encoding: [0xc5,0xf8,0x91,0x07]
+; X64-NEXT: kmovw %k1, (%rsi) # encoding: [0xc5,0xf8,0x91,0x0e]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = bitcast <8 x i64> %a to <16 x i32>
+ %1 = bitcast <8 x i64> %b to <16 x i32>
+ %2 = tail call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %0, <16 x i32> %1)
+ %3 = extractvalue { <16 x i1>, <16 x i1> } %2, 0
+ %4 = bitcast i16* %m0 to <16 x i1>*
+ store <16 x i1> %3, <16 x i1>* %4, align 16
+ %5 = extractvalue { <16 x i1>, <16 x i1> } %2, 1
+ %6 = bitcast i16* %m1 to <16 x i1>*
+ store <16 x i1> %5, <16 x i1>* %6, align 16
+ ret void
+}
+
+define void @test_mm512_2intersect_epi64(<8 x i64> %a, <8 x i64> %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm512_2intersect_epi64:
+; X86: # %bb.0: # %entry
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vp2intersectq %zmm1, %zmm0, %k0 # encoding: [0x62,0xf2,0xff,0x48,0x68,0xc1]
+; X86-NEXT: kmovw %k1, %ecx # encoding: [0xc5,0xf8,0x93,0xc9]
+; X86-NEXT: kmovw %k0, %edx # encoding: [0xc5,0xf8,0x93,0xd0]
+; X86-NEXT: movb %dl, (%eax) # encoding: [0x88,0x10]
+; X86-NEXT: movl 8(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm512_2intersect_epi64:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vp2intersectq %zmm1, %zmm0, %k0 # encoding: [0x62,0xf2,0xff,0x48,0x68,0xc1]
+; X64-NEXT: kmovw %k1, %eax # encoding: [0xc5,0xf8,0x93,0xc1]
+; X64-NEXT: kmovw %k0, %ecx # encoding: [0xc5,0xf8,0x93,0xc8]
+; X64-NEXT: movb %cl, (%rdi) # encoding: [0x88,0x0f]
+; X64-NEXT: movb %al, (%rsi) # encoding: [0x88,0x06]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = tail call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.q.512(<8 x i64> %a, <8 x i64> %b)
+ %1 = extractvalue { <8 x i1>, <8 x i1> } %0, 0
+ %2 = bitcast i8* %m0 to <8 x i1>*
+ store <8 x i1> %1, <8 x i1>* %2, align 8
+ %3 = extractvalue { <8 x i1>, <8 x i1> } %0, 1
+ %4 = bitcast i8* %m1 to <8 x i1>*
+ store <8 x i1> %3, <8 x i1>* %4, align 8
+ ret void
+}
+
+define void @test_mm512_2intersect_epi32_p(<8 x i64>* nocapture readonly %a, <8 x i64>* nocapture readonly %b, i16* nocapture %m0, i16* nocapture %m1) {
+; X86-LABEL: test_mm512_2intersect_epi32_p:
+; X86: # %bb.0: # %entry
+; X86-NEXT: pushl %esi # encoding: [0x56]
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %esi, -8
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x14]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x10]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx # encoding: [0x8b,0x54,0x24,0x0c]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi # encoding: [0x8b,0x74,0x24,0x08]
+; X86-NEXT: vmovaps (%esi), %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0x06]
+; X86-NEXT: vp2intersectd (%edx), %zmm0, %k0 # encoding: [0x62,0xf2,0x7f,0x48,0x68,0x02]
+; X86-NEXT: kmovw %k0, (%ecx) # encoding: [0xc5,0xf8,0x91,0x01]
+; X86-NEXT: kmovw %k1, (%eax) # encoding: [0xc5,0xf8,0x91,0x08]
+; X86-NEXT: popl %esi # encoding: [0x5e]
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm512_2intersect_epi32_p:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vmovaps (%rdi), %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0x07]
+; X64-NEXT: vp2intersectd (%rsi), %zmm0, %k0 # encoding: [0x62,0xf2,0x7f,0x48,0x68,0x06]
+; X64-NEXT: kmovw %k0, (%rdx) # encoding: [0xc5,0xf8,0x91,0x02]
+; X64-NEXT: kmovw %k1, (%rcx) # encoding: [0xc5,0xf8,0x91,0x09]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = bitcast <8 x i64>* %a to <16 x i32>*
+ %1 = load <16 x i32>, <16 x i32>* %0, align 64
+ %2 = bitcast <8 x i64>* %b to <16 x i32>*
+ %3 = load <16 x i32>, <16 x i32>* %2, align 64
+ %4 = tail call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %1, <16 x i32> %3)
+ %5 = extractvalue { <16 x i1>, <16 x i1> } %4, 0
+ %6 = bitcast i16* %m0 to <16 x i1>*
+ store <16 x i1> %5, <16 x i1>* %6, align 16
+ %7 = extractvalue { <16 x i1>, <16 x i1> } %4, 1
+ %8 = bitcast i16* %m1 to <16 x i1>*
+ store <16 x i1> %7, <16 x i1>* %8, align 16
+ ret void
+}
+
+define void @test_mm512_2intersect_epi64_p(<8 x i64>* nocapture readonly %a, <8 x i64>* nocapture readonly %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm512_2intersect_epi64_p:
+; X86: # %bb.0: # %entry
+; X86-NEXT: movl 12(%esp), %eax # encoding: [0x8b,0x44,0x24,0x0c]
+; X86-NEXT: movl 8(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x08]
+; X86-NEXT: movl 4(%esp), %edx # encoding: [0x8b,0x54,0x24,0x04]
+; X86-NEXT: vmovaps (%edx), %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0x02]
+; X86-NEXT: vp2intersectq (%ecx), %zmm0, %k0 # encoding: [0x62,0xf2,0xff,0x48,0x68,0x01]
+; X86-NEXT: kmovw %k1, %ecx # encoding: [0xc5,0xf8,0x93,0xc9]
+; X86-NEXT: kmovw %k0, %edx # encoding: [0xc5,0xf8,0x93,0xd0]
+; X86-NEXT: movb %dl, (%eax) # encoding: [0x88,0x10]
+; X86-NEXT: movl 16(%esp), %eax # encoding: [0x8b,0x44,0x24,0x10]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl
+
+;
+; X64-LABEL: test_mm512_2intersect_epi64_p:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vmovaps (%rdi), %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0x07]
+; X64-NEXT: vp2intersectq (%rsi), %zmm0, %k0 # encoding: [0x62,0xf2,0xff,0x48,0x68,0x06]
+; X64-NEXT: kmovw %k1, %eax # encoding: [0xc5,0xf8,0x93,0xc1]
+; X64-NEXT: kmovw %k0, %esi # encoding: [0xc5,0xf8,0x93,0xf0]
+; X64-NEXT: movb %sil, (%rdx) # encoding: [0x40,0x88,0x32]
+; X64-NEXT: movb %al, (%rcx) # encoding: [0x88,0x01]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = load <8 x i64>, <8 x i64>* %a, align 64
+ %1 = load <8 x i64>, <8 x i64>* %b, align 64
+ %2 = tail call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.q.512(<8 x i64> %0, <8 x i64> %1)
+ %3 = extractvalue { <8 x i1>, <8 x i1> } %2, 0
+ %4 = bitcast i8* %m0 to <8 x i1>*
+ store <8 x i1> %3, <8 x i1>* %4, align 8
+ %5 = extractvalue { <8 x i1>, <8 x i1> } %2, 1
+ %6 = bitcast i8* %m1 to <8 x i1>*
+ store <8 x i1> %5, <8 x i1>* %6, align 8
+ ret void
+}
+
+define void @test_mm512_2intersect_epi32_b(i32* nocapture readonly %a, i32* nocapture readonly %b, i16* nocapture %m0, i16* nocapture %m1) {
+; X86-LABEL: test_mm512_2intersect_epi32_b:
+; X86: # %bb.0: # %entry
+; X86-NEXT: pushl %esi # encoding: [0x56]
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %esi, -8
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x14]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x10]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx # encoding: [0x8b,0x54,0x24,0x0c]
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi # encoding: [0x8b,0x74,0x24,0x08]
+; X86-NEXT: vbroadcastss (%esi), %zmm0 # encoding: [0x62,0xf2,0x7d,0x48,0x18,0x06]
+; X86-NEXT: vp2intersectd (%edx){1to16}, %zmm0, %k0 # encoding: [0x62,0xf2,0x7f,0x58,0x68,0x02]
+; X86-NEXT: kmovw %k0, (%ecx) # encoding: [0xc5,0xf8,0x91,0x01]
+; X86-NEXT: kmovw %k1, (%eax) # encoding: [0xc5,0xf8,0x91,0x08]
+; X86-NEXT: popl %esi # encoding: [0x5e]
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm512_2intersect_epi32_b:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vbroadcastss (%rdi), %zmm0 # encoding: [0x62,0xf2,0x7d,0x48,0x18,0x07]
+; X64-NEXT: vp2intersectd (%rsi){1to16}, %zmm0, %k0 # encoding: [0x62,0xf2,0x7f,0x58,0x68,0x06]
+; X64-NEXT: kmovw %k0, (%rdx) # encoding: [0xc5,0xf8,0x91,0x02]
+; X64-NEXT: kmovw %k1, (%rcx) # encoding: [0xc5,0xf8,0x91,0x09]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = load i32, i32* %a, align 4
+ %vecinit.i = insertelement <16 x i32> undef, i32 %0, i32 0
+ %vecinit15.i = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+ %1 = load i32, i32* %b, align 4
+ %vecinit.i2 = insertelement <16 x i32> undef, i32 %1, i32 0
+ %vecinit15.i3 = shufflevector <16 x i32> %vecinit.i2, <16 x i32> undef, <16 x i32> zeroinitializer
+ %2 = tail call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %vecinit15.i, <16 x i32> %vecinit15.i3)
+ %3 = extractvalue { <16 x i1>, <16 x i1> } %2, 0
+ %4 = bitcast i16* %m0 to <16 x i1>*
+ store <16 x i1> %3, <16 x i1>* %4, align 16
+ %5 = extractvalue { <16 x i1>, <16 x i1> } %2, 1
+ %6 = bitcast i16* %m1 to <16 x i1>*
+ store <16 x i1> %5, <16 x i1>* %6, align 16
+ ret void
+}
+
+define void @test_mm512_2intersect_epi64_b(i64* nocapture readonly %a, i64* nocapture readonly %b, i8* nocapture %m0, i8* nocapture %m1) {
+; X86-LABEL: test_mm512_2intersect_epi64_b:
+; X86: # %bb.0: # %entry
+; X86-NEXT: movl 12(%esp), %eax # encoding: [0x8b,0x44,0x24,0x0c]
+; X86-NEXT: movl 8(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x08]
+; X86-NEXT: movl 4(%esp), %edx # encoding: [0x8b,0x54,0x24,0x04]
+; X86-NEXT: vbroadcastsd (%edx), %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x19,0x02]
+; X86-NEXT: vbroadcastsd (%ecx), %zmm1 # encoding: [0x62,0xf2,0xfd,0x48,0x19,0x09]
+; X86-NEXT: vp2intersectq %zmm1, %zmm0, %k0 # encoding: [0x62,0xf2,0xff,0x48,0x68,0xc1]
+; X86-NEXT: kmovw %k1, %ecx # encoding: [0xc5,0xf8,0x93,0xc9]
+; X86-NEXT: kmovw %k0, %edx # encoding: [0xc5,0xf8,0x93,0xd0]
+; X86-NEXT: movb %dl, (%eax) # encoding: [0x88,0x10]
+; X86-NEXT: movl 16(%esp), %eax # encoding: [0x8b,0x44,0x24,0x10]
+; X86-NEXT: movb %cl, (%eax) # encoding: [0x88,0x08]
+; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl # encoding: [0xc3]
+;
+; X64-LABEL: test_mm512_2intersect_epi64_b:
+; X64: # %bb.0: # %entry
+; X64-NEXT: vbroadcastsd (%rdi), %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x19,0x07]
+; X64-NEXT: vp2intersectq (%rsi){1to8}, %zmm0, %k0 # encoding: [0x62,0xf2,0xff,0x58,0x68,0x06]
+; X64-NEXT: kmovw %k1, %eax # encoding: [0xc5,0xf8,0x93,0xc1]
+; X64-NEXT: kmovw %k0, %esi # encoding: [0xc5,0xf8,0x93,0xf0]
+; X64-NEXT: movb %sil, (%rdx) # encoding: [0x40,0x88,0x32]
+; X64-NEXT: movb %al, (%rcx) # encoding: [0x88,0x01]
+; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq # encoding: [0xc3]
+entry:
+ %0 = load i64, i64* %a, align 8
+ %vecinit.i = insertelement <8 x i64> undef, i64 %0, i32 0
+ %vecinit7.i = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+ %1 = load i64, i64* %b, align 8
+ %vecinit.i2 = insertelement <8 x i64> undef, i64 %1, i32 0
+ %vecinit7.i3 = shufflevector <8 x i64> %vecinit.i2, <8 x i64> undef, <8 x i32> zeroinitializer
+ %2 = tail call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.q.512(<8 x i64> %vecinit7.i, <8 x i64> %vecinit7.i3)
+ %3 = extractvalue { <8 x i1>, <8 x i1> } %2, 0
+ %4 = bitcast i8* %m0 to <8 x i1>*
+ store <8 x i1> %3, <8 x i1>* %4, align 8
+ %5 = extractvalue { <8 x i1>, <8 x i1> } %2, 1
+ %6 = bitcast i8* %m1 to <8 x i1>*
+ store <8 x i1> %5, <8 x i1>* %6, align 8
+ ret void
+}
+
+declare { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32>, <16 x i32>)
+declare { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.q.512(<8 x i64>, <8 x i64>)
Modified: llvm/trunk/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll Thu May 30 19:50:41 2019
@@ -2,7 +2,8 @@
; CHECK: %[[REG1:.*]]:vr512_0_15 = COPY %1
; CHECK: %[[REG2:.*]]:vr512_0_15 = COPY %2
-; CHECK: INLINEASM &"vpaddq\09$3, $2, $0 {$1}", 0, 7340042, def %{{.*}}, 1179657, %{{.*}}, 7340041, %[[REG1]], 7340041, %[[REG2]], 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags
+; CHECK: INLINEASM &"vpaddq\09$3, $2, $0 {$1}", 0, {{.*}}, def %{{.*}}, {{.*}}, %{{.*}}, {{.*}}, %[[REG1]], {{.*}}, %[[REG2]], 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags
+
define <8 x i64> @mask_Yk_i8(i8 signext %msk, <8 x i64> %x, <8 x i64> %y) {
entry:
%0 = tail call <8 x i64> asm "vpaddq\09$3, $2, $0 {$1}", "=x,^Yk,x,x,~{dirflag},~{fpsr},~{flags}"(i8 %msk, <8 x i64> %x, <8 x i64> %y)
Added: llvm/trunk/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vp2intersect_multiple_pairs.ll?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vp2intersect_multiple_pairs.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vp2intersect_multiple_pairs.ll Thu May 30 19:50:41 2019
@@ -0,0 +1,150 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vp2intersect | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vp2intersect | FileCheck %s --check-prefixes=CHECK,X64
+
+; Test with more than four live mask pairs
+
+define void @test(<16 x i32> %a0, <16 x i32> %b0,
+ <16 x i32> %a1, <16 x i32> %b1,
+ <16 x i32> %a2, <16 x i32> %b2,
+ <16 x i32> %a3, <16 x i32> %b3,
+ <16 x i32> %a4, <16 x i32> %b4,
+ i16* nocapture %m0, i16* nocapture %m1) {
+; X86-LABEL: test:
+; X86: # %bb.0: # %entry
+; X86-NEXT: pushl %ebp
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %ebp, -8
+; X86-NEXT: movl %esp, %ebp
+; X86-NEXT: .cfi_def_cfa_register %ebp
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: andl $-64, %esp
+; X86-NEXT: subl $64, %esp
+; X86-NEXT: .cfi_offset %esi, -16
+; X86-NEXT: .cfi_offset %edi, -12
+; X86-NEXT: movl 456(%ebp), %esi
+; X86-NEXT: vmovaps 328(%ebp), %zmm3
+; X86-NEXT: vmovaps 200(%ebp), %zmm4
+; X86-NEXT: vmovaps 72(%ebp), %zmm5
+; X86-NEXT: vp2intersectd %zmm1, %zmm0, %k0
+; X86-NEXT: kmovw %k0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: kmovw %k1, {{[0-9]+}}(%esp)
+; X86-NEXT: vp2intersectd 8(%ebp), %zmm2, %k0
+; X86-NEXT: kmovw %k0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: kmovw %k1, {{[0-9]+}}(%esp)
+; X86-NEXT: vp2intersectd 136(%ebp), %zmm5, %k0
+; X86-NEXT: kmovw %k0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: kmovw %k1, {{[0-9]+}}(%esp)
+; X86-NEXT: vp2intersectd 264(%ebp), %zmm4, %k0
+; X86-NEXT: kmovw %k0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: kmovw %k1, {{[0-9]+}}(%esp)
+; X86-NEXT: vp2intersectd 392(%ebp), %zmm3, %k0
+; X86-NEXT: kmovw %k0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: kmovw %k1, {{[0-9]+}}(%esp)
+; X86-NEXT: vzeroupper
+; X86-NEXT: calll dummy
+; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k0 # 4-byte Folded Reload
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1
+; X86-NEXT: kmovw %k0, %eax
+; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k0 # 4-byte Folded Reload
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1
+; X86-NEXT: kmovw %k0, %ecx
+; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k0 # 4-byte Folded Reload
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1
+; X86-NEXT: kmovw %k0, %edx
+; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k0 # 4-byte Folded Reload
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1
+; X86-NEXT: kmovw %k0, %edi
+; X86-NEXT: addl %edi, %eax
+; X86-NEXT: kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k2 # 4-byte Folded Reload
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k3
+; X86-NEXT: kmovw %k2, %edi
+; X86-NEXT: addl %ecx, %edx
+; X86-NEXT: kmovw %k1, %ecx
+;
+; X64-LABEL: test:
+; X64: # %bb.0: # %entry
+; X64-NEXT: pushq %rbp
+; X64-NEXT: .cfi_def_cfa_offset 16
+; X64-NEXT: .cfi_offset %rbp, -16
+; X64-NEXT: movq %rsp, %rbp
+; X64-NEXT: .cfi_def_cfa_register %rbp
+; X64-NEXT: pushq %r14
+; X64-NEXT: pushq %rbx
+; X64-NEXT: andq $-64, %rsp
+; X64-NEXT: subq $64, %rsp
+; X64-NEXT: .cfi_offset %rbx, -32
+; X64-NEXT: .cfi_offset %r14, -24
+; X64-NEXT: movq %rdi, %r14
+; X64-NEXT: vmovaps 16(%rbp), %zmm8
+; X64-NEXT: vp2intersectd %zmm1, %zmm0, %k0
+; X64-NEXT: kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
+; X64-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
+; X64-NEXT: vp2intersectd %zmm3, %zmm2, %k0
+; X64-NEXT: kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
+; X64-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
+; X64-NEXT: vp2intersectd %zmm5, %zmm4, %k0
+; X64-NEXT: kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
+; X64-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
+; X64-NEXT: vp2intersectd %zmm7, %zmm6, %k0
+; X64-NEXT: kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
+; X64-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
+; X64-NEXT: vp2intersectd 80(%rbp), %zmm8, %k0
+; X64-NEXT: kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
+; X64-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
+; X64-NEXT: vzeroupper
+; X64-NEXT: callq dummy
+; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 4-byte Folded Reload
+; X64-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
+; X64-NEXT: kmovw %k0, %eax
+; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 4-byte Folded Reload
+; X64-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
+; X64-NEXT: kmovw %k0, %ecx
+; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 4-byte Folded Reload
+; X64-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
+; X64-NEXT: kmovw %k0, %edx
+; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 4-byte Folded Reload
+; X64-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
+; X64-NEXT: kmovw %k0, %esi
+; X64-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 4-byte Folded Reload
+; X64-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
+; X64-NEXT: kmovw %k0, %edi
+; X64-NEXT: kmovw %k1, %ebx
+entry:
+ %0 = call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %a0, <16 x i32> %b0)
+ %1 = call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %a1, <16 x i32> %b1)
+ %2 = call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %a2, <16 x i32> %b2)
+ %3 = call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %a3, <16 x i32> %b3)
+ %4 = call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %a4, <16 x i32> %b4)
+
+ %5 = extractvalue { <16 x i1>, <16 x i1> } %0, 0
+ %6 = extractvalue { <16 x i1>, <16 x i1> } %1, 0
+ %7 = extractvalue { <16 x i1>, <16 x i1> } %2, 0
+ %8 = extractvalue { <16 x i1>, <16 x i1> } %3, 0
+ %9 = extractvalue { <16 x i1>, <16 x i1> } %4, 0
+ %10 = extractvalue { <16 x i1>, <16 x i1> } %0, 1
+ %11 = extractvalue { <16 x i1>, <16 x i1> } %1, 1
+
+ call void @dummy()
+
+ %12 = bitcast <16 x i1> %5 to i16
+ %13 = bitcast <16 x i1> %6 to i16
+ %14 = bitcast <16 x i1> %7 to i16
+ %15 = bitcast <16 x i1> %8 to i16
+ %16 = bitcast <16 x i1> %9 to i16
+ %17 = bitcast <16 x i1> %10 to i16
+ %18 = bitcast <16 x i1> %11 to i16
+
+ %19 = add i16 %12, %13
+ %20 = add i16 %14, %15
+ %21 = add i16 %16, %17
+ %22 = add i16 %19, %21
+ %23 = add i16 %22, %20
+
+ store i16 %23, i16* %m0, align 16
+ ret void
+}
+
+declare { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32>, <16 x i32>)
+declare void @dummy()
Added: llvm/trunk/test/MC/Disassembler/X86/avx512-vp2intersect-32-att.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/avx512-vp2intersect-32-att.txt?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/avx512-vp2intersect-32-att.txt (added)
+++ llvm/trunk/test/MC/Disassembler/X86/avx512-vp2intersect-32-att.txt Thu May 30 19:50:41 2019
@@ -0,0 +1,16 @@
+# RUN: llvm-mc --disassemble %s -triple=i686-apple-darwin9 | FileCheck %s
+
+# Coverage
+#CHECK: vp2intersectq %zmm2, %zmm1, %k0
+0x62 0xf2 0xf7 0x48 0x68 0xc2
+
+# Instruction encodes k1, but we print k0 anyways.
+# Not sure if GNU binutils does the same.
+#CHECK: vp2intersectq %zmm2, %zmm1, %k0
+0x62 0xf2 0xf7 0x48 0x68 0xca
+
+#CHECK: vp2intersectq (%esi){1to8}, %zmm4, %k6
+0x62 0xf2 0xdf 0x58 0x68 0x36
+
+#CHECK: vp2intersectd %xmm7, %xmm4, %k6
+0x62 0xf2 0x5f 0x08 0x68 0xff
Added: llvm/trunk/test/MC/Disassembler/X86/avx512-vp2intersect-64-att.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/avx512-vp2intersect-64-att.txt?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/avx512-vp2intersect-64-att.txt (added)
+++ llvm/trunk/test/MC/Disassembler/X86/avx512-vp2intersect-64-att.txt Thu May 30 19:50:41 2019
@@ -0,0 +1,16 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s
+
+# Coverage
+#CHECK: vp2intersectq %zmm2, %zmm1, %k0
+0x62 0xf2 0xf7 0x48 0x68 0xc2
+
+# Instruction encodes k1, but we print k0 anyways.
+# Not sure if GNU binutils does the same.
+#CHECK: vp2intersectq %zmm2, %zmm1, %k0
+0x62 0xf2 0xf7 0x48 0x68 0xca
+
+#CHECK: vp2intersectq (%rsi){1to8}, %zmm9, %k6
+0x62 0xf2 0xb7 0x58 0x68 0x36
+
+#CHECK: vp2intersectd %xmm7, %xmm9, %k6
+0x62 0xf2 0x37 0x08 0x68 0xff
Added: llvm/trunk/test/MC/Disassembler/X86/avx512_vp2intersect-32-intel.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/avx512_vp2intersect-32-intel.txt?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/avx512_vp2intersect-32-intel.txt (added)
+++ llvm/trunk/test/MC/Disassembler/X86/avx512_vp2intersect-32-intel.txt Thu May 30 19:50:41 2019
@@ -0,0 +1,43 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s
+# CHECK: vp2intersectd k4, zmm3, zmm4
+0x62,0xf2,0x67,0x48,0x68,0xe4
+
+# CHECK: vp2intersectd k4, zmm3, zmmword ptr [esp + 8*esi + 268435456]
+0x62,0xf2,0x67,0x48,0x68,0xa4,0xf4,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectd k4, zmm3, zmmword ptr [edi + 4*eax + 291]
+0x62,0xf2,0x67,0x48,0x68,0xa4,0x87,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectd k4, zmm3, dword ptr [eax]{1to16}
+0x62,0xf2,0x67,0x58,0x68,0x20
+
+# CHECK: vp2intersectd k4, zmm3, zmmword ptr [2*ebp - 2048]
+0x62,0xf2,0x67,0x48,0x68,0x24,0x6d,0x00,0xf8,0xff,0xff
+
+# CHECK: vp2intersectd k4, zmm3, zmmword ptr [ecx + 8128]
+0x62,0xf2,0x67,0x48,0x68,0x61,0x7f
+
+# CHECK: vp2intersectd k4, zmm3, dword ptr [edx - 512]{1to16}
+0x62,0xf2,0x67,0x58,0x68,0x62,0x80
+
+# CHECK: vp2intersectq k4, zmm3, zmm4
+0x62,0xf2,0xe7,0x48,0x68,0xe4
+
+# CHECK: vp2intersectq k4, zmm3, zmmword ptr [esp + 8*esi + 268435456]
+0x62,0xf2,0xe7,0x48,0x68,0xa4,0xf4,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectq k4, zmm3, zmmword ptr [edi + 4*eax + 291]
+0x62,0xf2,0xe7,0x48,0x68,0xa4,0x87,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectq k4, zmm3, qword ptr [eax]{1to8}
+0x62,0xf2,0xe7,0x58,0x68,0x20
+
+# CHECK: vp2intersectq k4, zmm3, zmmword ptr [2*ebp - 2048]
+0x62,0xf2,0xe7,0x48,0x68,0x24,0x6d,0x00,0xf8,0xff,0xff
+
+# CHECK: vp2intersectq k4, zmm3, zmmword ptr [ecx + 8128]
+0x62,0xf2,0xe7,0x48,0x68,0x61,0x7f
+
+# CHECK: vp2intersectq k4, zmm3, qword ptr [edx - 1024]{1to8}
+0x62,0xf2,0xe7,0x58,0x68,0x62,0x80
+
Added: llvm/trunk/test/MC/Disassembler/X86/avx512_vp2intersect-64-intel.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/avx512_vp2intersect-64-intel.txt?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/avx512_vp2intersect-64-intel.txt (added)
+++ llvm/trunk/test/MC/Disassembler/X86/avx512_vp2intersect-64-intel.txt Thu May 30 19:50:41 2019
@@ -0,0 +1,43 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s
+# CHECK: vp2intersectd k4, zmm23, zmm24
+0x62,0x92,0x47,0x40,0x68,0xe0
+
+# CHECK: vp2intersectd k4, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
+0x62,0xb2,0x47,0x40,0x68,0xa4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectd k4, zmm23, zmmword ptr [r8 + 4*rax + 291]
+0x62,0xd2,0x47,0x40,0x68,0xa4,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectd k4, zmm23, dword ptr [rip]{1to16}
+0x62,0xf2,0x47,0x50,0x68,0x25,0x00,0x00,0x00,0x00
+
+# CHECK: vp2intersectd k4, zmm23, zmmword ptr [2*rbp - 2048]
+0x62,0xf2,0x47,0x40,0x68,0x24,0x6d,0x00,0xf8,0xff,0xff
+
+# CHECK: vp2intersectd k4, zmm23, zmmword ptr [rcx + 8128]
+0x62,0xf2,0x47,0x40,0x68,0x61,0x7f
+
+# CHECK: vp2intersectd k4, zmm23, dword ptr [rdx - 512]{1to16}
+0x62,0xf2,0x47,0x50,0x68,0x62,0x80
+
+# CHECK: vp2intersectq k4, zmm23, zmm24
+0x62,0x92,0xc7,0x40,0x68,0xe0
+
+# CHECK: vp2intersectq k4, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
+0x62,0xb2,0xc7,0x40,0x68,0xa4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectq k4, zmm23, zmmword ptr [r8 + 4*rax + 291]
+0x62,0xd2,0xc7,0x40,0x68,0xa4,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectq k4, zmm23, qword ptr [rip]{1to8}
+0x62,0xf2,0xc7,0x50,0x68,0x25,0x00,0x00,0x00,0x00
+
+# CHECK: vp2intersectq k4, zmm23, zmmword ptr [2*rbp - 2048]
+0x62,0xf2,0xc7,0x40,0x68,0x24,0x6d,0x00,0xf8,0xff,0xff
+
+# CHECK: vp2intersectq k4, zmm23, zmmword ptr [rcx + 8128]
+0x62,0xf2,0xc7,0x40,0x68,0x61,0x7f
+
+# CHECK: vp2intersectq k4, zmm23, qword ptr [rdx - 1024]{1to8}
+0x62,0xf2,0xc7,0x50,0x68,0x62,0x80
+
Added: llvm/trunk/test/MC/Disassembler/X86/avx512vp2intersectvl-att.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/avx512vp2intersectvl-att.txt?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/avx512vp2intersectvl-att.txt (added)
+++ llvm/trunk/test/MC/Disassembler/X86/avx512vp2intersectvl-att.txt Thu May 30 19:50:41 2019
@@ -0,0 +1,86 @@
+# RUN: llvm-mc --disassemble %s -triple=i686-apple-darwin9 | FileCheck %s
+
+# CHECK: vp2intersectd %ymm4, %ymm3, %k6
+0x62,0xf2,0x67,0x28,0x68,0xf4
+
+# CHECK: vp2intersectd %xmm4, %xmm3, %k6
+0x62,0xf2,0x67,0x08,0x68,0xf4
+
+# CHECK: vp2intersectd 268435456(%esp,%esi,8), %ymm3, %k6
+0x62,0xf2,0x67,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectd 291(%edi,%eax,4), %ymm3, %k6
+0x62,0xf2,0x67,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectd (%eax){1to8}, %ymm3, %k6
+0x62,0xf2,0x67,0x38,0x68,0x30
+
+# CHECK: vp2intersectd -1024(,%ebp,2), %ymm3, %k6
+0x62,0xf2,0x67,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff
+
+# CHECK: vp2intersectd 4064(%ecx), %ymm3, %k6
+0x62,0xf2,0x67,0x28,0x68,0x71,0x7f
+
+# CHECK: vp2intersectd -512(%edx){1to8}, %ymm3, %k6
+0x62,0xf2,0x67,0x38,0x68,0x72,0x80
+
+# CHECK: vp2intersectd 268435456(%esp,%esi,8), %xmm3, %k6
+0x62,0xf2,0x67,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectd 291(%edi,%eax,4), %xmm3, %k6
+0x62,0xf2,0x67,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectd (%eax){1to4}, %xmm3, %k6
+0x62,0xf2,0x67,0x18,0x68,0x30
+
+# CHECK: vp2intersectd -512(,%ebp,2), %xmm3, %k6
+0x62,0xf2,0x67,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff
+
+# CHECK: vp2intersectd 2032(%ecx), %xmm3, %k6
+0x62,0xf2,0x67,0x08,0x68,0x71,0x7f
+
+# CHECK: vp2intersectd -512(%edx){1to4}, %xmm3, %k6
+0x62,0xf2,0x67,0x18,0x68,0x72,0x80
+
+# CHECK: vp2intersectq %ymm4, %ymm3, %k6
+0x62,0xf2,0xe7,0x28,0x68,0xf4
+
+# CHECK: vp2intersectq %xmm4, %xmm3, %k6
+0x62,0xf2,0xe7,0x08,0x68,0xf4
+
+# CHECK: vp2intersectq 268435456(%esp,%esi,8), %ymm3, %k6
+0x62,0xf2,0xe7,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectq 291(%edi,%eax,4), %ymm3, %k6
+0x62,0xf2,0xe7,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectq (%eax){1to4}, %ymm3, %k6
+0x62,0xf2,0xe7,0x38,0x68,0x30
+
+# CHECK: vp2intersectq -1024(,%ebp,2), %ymm3, %k6
+0x62,0xf2,0xe7,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff
+
+# CHECK: vp2intersectq 4064(%ecx), %ymm3, %k6
+0x62,0xf2,0xe7,0x28,0x68,0x71,0x7f
+
+# CHECK: vp2intersectq -1024(%edx){1to4}, %ymm3, %k6
+0x62,0xf2,0xe7,0x38,0x68,0x72,0x80
+
+# CHECK: vp2intersectq 268435456(%esp,%esi,8), %xmm3, %k6
+0x62,0xf2,0xe7,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectq 291(%edi,%eax,4), %xmm3, %k6
+0x62,0xf2,0xe7,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectq (%eax){1to2}, %xmm3, %k6
+0x62,0xf2,0xe7,0x18,0x68,0x30
+
+# CHECK: vp2intersectq -512(,%ebp,2), %xmm3, %k6
+0x62,0xf2,0xe7,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff
+
+# CHECK: vp2intersectq 2032(%ecx), %xmm3, %k6
+0x62,0xf2,0xe7,0x08,0x68,0x71,0x7f
+
+# CHECK: vp2intersectq -1024(%edx){1to2}, %xmm3, %k6
+0x62,0xf2,0xe7,0x18,0x68,0x72,0x80
+
Added: llvm/trunk/test/MC/Disassembler/X86/avx512vp2intersectvl-intel.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/avx512vp2intersectvl-intel.txt?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/avx512vp2intersectvl-intel.txt (added)
+++ llvm/trunk/test/MC/Disassembler/X86/avx512vp2intersectvl-intel.txt Thu May 30 19:50:41 2019
@@ -0,0 +1,85 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s
+
+# CHECK: vp2intersectd k6, ymm3, ymm4
+0x62,0xf2,0x67,0x28,0x68,0xf4
+
+# CHECK: vp2intersectd k6, xmm3, xmm4
+0x62,0xf2,0x67,0x08,0x68,0xf4
+
+# CHECK: vp2intersectd k6, ymm3, ymmword ptr [esp + 8*esi + 268435456]
+0x62,0xf2,0x67,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectd k6, ymm3, ymmword ptr [edi + 4*eax + 291]
+0x62,0xf2,0x67,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectd k6, ymm3, dword ptr [eax]{1to8}
+0x62,0xf2,0x67,0x38,0x68,0x30
+
+# CHECK: vp2intersectd k6, ymm3, ymmword ptr [2*ebp - 1024]
+0x62,0xf2,0x67,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff
+
+# CHECK: vp2intersectd k6, ymm3, ymmword ptr [ecx + 4064]
+0x62,0xf2,0x67,0x28,0x68,0x71,0x7f
+
+# CHECK: vp2intersectd k6, ymm3, dword ptr [edx - 512]{1to8}
+0x62,0xf2,0x67,0x38,0x68,0x72,0x80
+
+# CHECK: vp2intersectd k6, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+0x62,0xf2,0x67,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectd k6, xmm3, xmmword ptr [edi + 4*eax + 291]
+0x62,0xf2,0x67,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectd k6, xmm3, dword ptr [eax]{1to4}
+0x62,0xf2,0x67,0x18,0x68,0x30
+
+# CHECK: vp2intersectd k6, xmm3, xmmword ptr [2*ebp - 512]
+0x62,0xf2,0x67,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff
+
+# CHECK: vp2intersectd k6, xmm3, xmmword ptr [ecx + 2032]
+0x62,0xf2,0x67,0x08,0x68,0x71,0x7f
+
+# CHECK: vp2intersectd k6, xmm3, dword ptr [edx - 512]{1to4}
+0x62,0xf2,0x67,0x18,0x68,0x72,0x80
+
+# CHECK: vp2intersectq k6, ymm3, ymm4
+0x62,0xf2,0xe7,0x28,0x68,0xf4
+
+# CHECK: vp2intersectq k6, xmm3, xmm4
+0x62,0xf2,0xe7,0x08,0x68,0xf4
+
+# CHECK: vp2intersectq k6, ymm3, ymmword ptr [esp + 8*esi + 268435456]
+0x62,0xf2,0xe7,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectq k6, ymm3, ymmword ptr [edi + 4*eax + 291]
+0x62,0xf2,0xe7,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectq k6, ymm3, qword ptr [eax]{1to4}
+0x62,0xf2,0xe7,0x38,0x68,0x30
+
+# CHECK: vp2intersectq k6, ymm3, ymmword ptr [2*ebp - 1024]
+0x62,0xf2,0xe7,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff
+
+# CHECK: vp2intersectq k6, ymm3, ymmword ptr [ecx + 4064]
+0x62,0xf2,0xe7,0x28,0x68,0x71,0x7f
+
+# CHECK: vp2intersectq k6, ymm3, qword ptr [edx - 1024]{1to4}
+0x62,0xf2,0xe7,0x38,0x68,0x72,0x80
+
+# CHECK: vp2intersectq k6, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+0x62,0xf2,0xe7,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectq k6, xmm3, xmmword ptr [edi + 4*eax + 291]
+0x62,0xf2,0xe7,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectq k6, xmm3, qword ptr [eax]{1to2}
+0x62,0xf2,0xe7,0x18,0x68,0x30
+
+# CHECK: vp2intersectq k6, xmm3, xmmword ptr [2*ebp - 512]
+0x62,0xf2,0xe7,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff
+
+# CHECK: vp2intersectq k6, xmm3, xmmword ptr [ecx + 2032]
+0x62,0xf2,0xe7,0x08,0x68,0x71,0x7f
+
+# CHECK: vp2intersectq k6, xmm3, qword ptr [edx - 1024]{1to2}
+0x62,0xf2,0xe7,0x18,0x68,0x72,0x80
Added: llvm/trunk/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-att.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-att.txt?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-att.txt (added)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-att.txt Thu May 30 19:50:41 2019
@@ -0,0 +1,85 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s
+
+# CHECK: vp2intersectd %ymm24, %ymm23, %k6
+0x62,0x92,0x47,0x20,0x68,0xf0
+
+# CHECK: vp2intersectd %xmm24, %xmm23, %k6
+0x62,0x92,0x47,0x00,0x68,0xf0
+
+# CHECK: vp2intersectd 268435456(%rbp,%r14,8), %ymm23, %k6
+0x62,0xb2,0x47,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectd 291(%r8,%rax,4), %ymm23, %k6
+0x62,0xd2,0x47,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectd (%rip){1to8}, %ymm23, %k6
+0x62,0xf2,0x47,0x30,0x68,0x35,0x00,0x00,0x00,0x00
+
+# CHECK: vp2intersectd -1024(,%rbp,2), %ymm23, %k6
+0x62,0xf2,0x47,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff
+
+# CHECK: vp2intersectd 4064(%rcx), %ymm23, %k6
+0x62,0xf2,0x47,0x20,0x68,0x71,0x7f
+
+# CHECK: vp2intersectd -512(%rdx){1to8}, %ymm23, %k6
+0x62,0xf2,0x47,0x30,0x68,0x72,0x80
+
+# CHECK: vp2intersectd 268435456(%rbp,%r14,8), %xmm23, %k6
+0x62,0xb2,0x47,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectd 291(%r8,%rax,4), %xmm23, %k6
+0x62,0xd2,0x47,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectd (%rip){1to4}, %xmm23, %k6
+0x62,0xf2,0x47,0x10,0x68,0x35,0x00,0x00,0x00,0x00
+
+# CHECK: vp2intersectd -512(,%rbp,2), %xmm23, %k6
+0x62,0xf2,0x47,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff
+
+# CHECK: vp2intersectd 2032(%rcx), %xmm23, %k6
+0x62,0xf2,0x47,0x00,0x68,0x71,0x7f
+
+# CHECK: vp2intersectd -512(%rdx){1to4}, %xmm23, %k6
+0x62,0xf2,0x47,0x10,0x68,0x72,0x80
+
+# CHECK: vp2intersectq %ymm24, %ymm23, %k6
+0x62,0x92,0xc7,0x20,0x68,0xf0
+
+# CHECK: vp2intersectq %xmm24, %xmm23, %k6
+0x62,0x92,0xc7,0x00,0x68,0xf0
+
+# CHECK: vp2intersectq 268435456(%rbp,%r14,8), %ymm23, %k6
+0x62,0xb2,0xc7,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectq 291(%r8,%rax,4), %ymm23, %k6
+0x62,0xd2,0xc7,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectq (%rip){1to4}, %ymm23, %k6
+0x62,0xf2,0xc7,0x30,0x68,0x35,0x00,0x00,0x00,0x00
+
+# CHECK: vp2intersectq -1024(,%rbp,2), %ymm23, %k6
+0x62,0xf2,0xc7,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff
+
+# CHECK: vp2intersectq 4064(%rcx), %ymm23, %k6
+0x62,0xf2,0xc7,0x20,0x68,0x71,0x7f
+
+# CHECK: vp2intersectq -1024(%rdx){1to4}, %ymm23, %k6
+0x62,0xf2,0xc7,0x30,0x68,0x72,0x80
+
+# CHECK: vp2intersectq 268435456(%rbp,%r14,8), %xmm23, %k6
+0x62,0xb2,0xc7,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectq 291(%r8,%rax,4), %xmm23, %k6
+0x62,0xd2,0xc7,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectq (%rip){1to2}, %xmm23, %k6
+0x62,0xf2,0xc7,0x10,0x68,0x35,0x00,0x00,0x00,0x00
+
+# CHECK: vp2intersectq -512(,%rbp,2), %xmm23, %k6
+0x62,0xf2,0xc7,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff
+
+# CHECK: vp2intersectq 2032(%rcx), %xmm23, %k6
+0x62,0xf2,0xc7,0x00,0x68,0x71,0x7f
+
+# CHECK: vp2intersectq -1024(%rdx){1to2}, %xmm23, %k6
+0x62,0xf2,0xc7,0x10,0x68,0x72,0x80
Added: llvm/trunk/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-intel.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-intel.txt?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-intel.txt (added)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-intel.txt Thu May 30 19:50:41 2019
@@ -0,0 +1,85 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s
+
+# CHECK: vp2intersectd k6, ymm23, ymm24
+0x62,0x92,0x47,0x20,0x68,0xf0
+
+# CHECK: vp2intersectd k6, xmm23, xmm24
+0x62,0x92,0x47,0x00,0x68,0xf0
+
+# CHECK: vp2intersectd k6, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
+0x62,0xb2,0x47,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectd k6, ymm23, ymmword ptr [r8 + 4*rax + 291]
+0x62,0xd2,0x47,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectd k6, ymm23, dword ptr [rip]{1to8}
+0x62,0xf2,0x47,0x30,0x68,0x35,0x00,0x00,0x00,0x00
+
+# CHECK: vp2intersectd k6, ymm23, ymmword ptr [2*rbp - 1024]
+0x62,0xf2,0x47,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff
+
+# CHECK: vp2intersectd k6, ymm23, ymmword ptr [rcx + 4064]
+0x62,0xf2,0x47,0x20,0x68,0x71,0x7f
+
+# CHECK: vp2intersectd k6, ymm23, dword ptr [rdx - 512]{1to8}
+0x62,0xf2,0x47,0x30,0x68,0x72,0x80
+
+# CHECK: vp2intersectd k6, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
+0x62,0xb2,0x47,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectd k6, xmm23, xmmword ptr [r8 + 4*rax + 291]
+0x62,0xd2,0x47,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectd k6, xmm23, dword ptr [rip]{1to4}
+0x62,0xf2,0x47,0x10,0x68,0x35,0x00,0x00,0x00,0x00
+
+# CHECK: vp2intersectd k6, xmm23, xmmword ptr [2*rbp - 512]
+0x62,0xf2,0x47,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff
+
+# CHECK: vp2intersectd k6, xmm23, xmmword ptr [rcx + 2032]
+0x62,0xf2,0x47,0x00,0x68,0x71,0x7f
+
+# CHECK: vp2intersectd k6, xmm23, dword ptr [rdx - 512]{1to4}
+0x62,0xf2,0x47,0x10,0x68,0x72,0x80
+
+# CHECK: vp2intersectq k6, ymm23, ymm24
+0x62,0x92,0xc7,0x20,0x68,0xf0
+
+# CHECK: vp2intersectq k6, xmm23, xmm24
+0x62,0x92,0xc7,0x00,0x68,0xf0
+
+# CHECK: vp2intersectq k6, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
+0x62,0xb2,0xc7,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectq k6, ymm23, ymmword ptr [r8 + 4*rax + 291]
+0x62,0xd2,0xc7,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectq k6, ymm23, qword ptr [rip]{1to4}
+0x62,0xf2,0xc7,0x30,0x68,0x35,0x00,0x00,0x00,0x00
+
+# CHECK: vp2intersectq k6, ymm23, ymmword ptr [2*rbp - 1024]
+0x62,0xf2,0xc7,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff
+
+# CHECK: vp2intersectq k6, ymm23, ymmword ptr [rcx + 4064]
+0x62,0xf2,0xc7,0x20,0x68,0x71,0x7f
+
+# CHECK: vp2intersectq k6, ymm23, qword ptr [rdx - 1024]{1to4}
+0x62,0xf2,0xc7,0x30,0x68,0x72,0x80
+
+# CHECK: vp2intersectq k6, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
+0x62,0xb2,0xc7,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: vp2intersectq k6, xmm23, xmmword ptr [r8 + 4*rax + 291]
+0x62,0xd2,0xc7,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: vp2intersectq k6, xmm23, qword ptr [rip]{1to2}
+0x62,0xf2,0xc7,0x10,0x68,0x35,0x00,0x00,0x00,0x00
+
+# CHECK: vp2intersectq k6, xmm23, xmmword ptr [2*rbp - 512]
+0x62,0xf2,0xc7,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff
+
+# CHECK: vp2intersectq k6, xmm23, xmmword ptr [rcx + 2032]
+0x62,0xf2,0xc7,0x00,0x68,0x71,0x7f
+
+# CHECK: vp2intersectq k6, xmm23, qword ptr [rdx - 1024]{1to2}
+0x62,0xf2,0xc7,0x10,0x68,0x72,0x80
Added: llvm/trunk/test/MC/X86/avx512vp2intersectvl-att.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/avx512vp2intersectvl-att.s?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/avx512vp2intersectvl-att.s (added)
+++ llvm/trunk/test/MC/X86/avx512vp2intersectvl-att.s Thu May 30 19:50:41 2019
@@ -0,0 +1,113 @@
+// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK: vp2intersectd %ymm4, %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x28,0x68,0xf4]
+ vp2intersectd %ymm4, %ymm3, %k6
+
+// CHECK: vp2intersectd %xmm4, %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x08,0x68,0xf4]
+ vp2intersectd %xmm4, %xmm3, %k6
+
+// CHECK: vp2intersectd 268435456(%esp,%esi,8), %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10]
+ vp2intersectd 268435456(%esp,%esi,8), %ymm3, %k6
+
+// CHECK: vp2intersectd 291(%edi,%eax,4), %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00]
+ vp2intersectd 291(%edi,%eax,4), %ymm3, %k6
+
+// CHECK: vp2intersectd (%eax){1to8}, %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x38,0x68,0x30]
+ vp2intersectd (%eax){1to8}, %ymm3, %k6
+
+// CHECK: vp2intersectd -1024(,%ebp,2), %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff]
+ vp2intersectd -1024(,%ebp,2), %ymm3, %k6
+
+// CHECK: vp2intersectd 4064(%ecx), %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x28,0x68,0x71,0x7f]
+ vp2intersectd 4064(%ecx), %ymm3, %k6
+
+// CHECK: vp2intersectd -512(%edx){1to8}, %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x38,0x68,0x72,0x80]
+ vp2intersectd -512(%edx){1to8}, %ymm3, %k6
+
+// CHECK: vp2intersectd 268435456(%esp,%esi,8), %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10]
+ vp2intersectd 268435456(%esp,%esi,8), %xmm3, %k6
+
+// CHECK: vp2intersectd 291(%edi,%eax,4), %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00]
+ vp2intersectd 291(%edi,%eax,4), %xmm3, %k6
+
+// CHECK: vp2intersectd (%eax){1to4}, %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x18,0x68,0x30]
+ vp2intersectd (%eax){1to4}, %xmm3, %k6
+
+// CHECK: vp2intersectd -512(,%ebp,2), %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff]
+ vp2intersectd -512(,%ebp,2), %xmm3, %k6
+
+// CHECK: vp2intersectd 2032(%ecx), %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x08,0x68,0x71,0x7f]
+ vp2intersectd 2032(%ecx), %xmm3, %k6
+
+// CHECK: vp2intersectd -512(%edx){1to4}, %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0x67,0x18,0x68,0x72,0x80]
+ vp2intersectd -512(%edx){1to4}, %xmm3, %k6
+
+// CHECK: vp2intersectq %ymm4, %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x28,0x68,0xf4]
+ vp2intersectq %ymm4, %ymm3, %k6
+
+// CHECK: vp2intersectq %xmm4, %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x08,0x68,0xf4]
+ vp2intersectq %xmm4, %xmm3, %k6
+
+// CHECK: vp2intersectq 268435456(%esp,%esi,8), %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10]
+ vp2intersectq 268435456(%esp,%esi,8), %ymm3, %k6
+
+// CHECK: vp2intersectq 291(%edi,%eax,4), %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00]
+ vp2intersectq 291(%edi,%eax,4), %ymm3, %k6
+
+// CHECK: vp2intersectq (%eax){1to4}, %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x38,0x68,0x30]
+ vp2intersectq (%eax){1to4}, %ymm3, %k6
+
+// CHECK: vp2intersectq -1024(,%ebp,2), %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff]
+ vp2intersectq -1024(,%ebp,2), %ymm3, %k6
+
+// CHECK: vp2intersectq 4064(%ecx), %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x28,0x68,0x71,0x7f]
+ vp2intersectq 4064(%ecx), %ymm3, %k6
+
+// CHECK: vp2intersectq -1024(%edx){1to4}, %ymm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x38,0x68,0x72,0x80]
+ vp2intersectq -1024(%edx){1to4}, %ymm3, %k6
+
+// CHECK: vp2intersectq 268435456(%esp,%esi,8), %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10]
+ vp2intersectq 268435456(%esp,%esi,8), %xmm3, %k6
+
+// CHECK: vp2intersectq 291(%edi,%eax,4), %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00]
+ vp2intersectq 291(%edi,%eax,4), %xmm3, %k6
+
+// CHECK: vp2intersectq (%eax){1to2}, %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x18,0x68,0x30]
+ vp2intersectq (%eax){1to2}, %xmm3, %k6
+
+// CHECK: vp2intersectq -512(,%ebp,2), %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff]
+ vp2intersectq -512(,%ebp,2), %xmm3, %k6
+
+// CHECK: vp2intersectq 2032(%ecx), %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x08,0x68,0x71,0x7f]
+ vp2intersectq 2032(%ecx), %xmm3, %k6
+
+// CHECK: vp2intersectq -1024(%edx){1to2}, %xmm3, %k6
+// CHECK: encoding: [0x62,0xf2,0xe7,0x18,0x68,0x72,0x80]
+ vp2intersectq -1024(%edx){1to2}, %xmm3, %k6
Added: llvm/trunk/test/MC/X86/avx512vp2intersectvl-intel.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/avx512vp2intersectvl-intel.s?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/avx512vp2intersectvl-intel.s (added)
+++ llvm/trunk/test/MC/X86/avx512vp2intersectvl-intel.s Thu May 30 19:50:41 2019
@@ -0,0 +1,113 @@
+// RUN: llvm-mc -triple i386-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vp2intersectd k6, ymm3, ymm4
+// CHECK: encoding: [0x62,0xf2,0x67,0x28,0x68,0xf4]
+ vp2intersectd k6, ymm3, ymm4
+
+// CHECK: vp2intersectd k6, xmm3, xmm4
+// CHECK: encoding: [0x62,0xf2,0x67,0x08,0x68,0xf4]
+ vp2intersectd k6, xmm3, xmm4
+
+// CHECK: vp2intersectd k6, ymm3, ymmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0x62,0xf2,0x67,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10]
+ vp2intersectd k6, ymm3, ymmword ptr [esp + 8*esi + 268435456]
+
+// CHECK: vp2intersectd k6, ymm3, ymmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0x62,0xf2,0x67,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00]
+ vp2intersectd k6, ymm3, ymmword ptr [edi + 4*eax + 291]
+
+// CHECK: vp2intersectd k6, ymm3, dword ptr [eax]{1to8}
+// CHECK: encoding: [0x62,0xf2,0x67,0x38,0x68,0x30]
+ vp2intersectd k6, ymm3, dword ptr [eax]{1to8}
+
+// CHECK: vp2intersectd k6, ymm3, ymmword ptr [2*ebp - 1024]
+// CHECK: encoding: [0x62,0xf2,0x67,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff]
+ vp2intersectd k6, ymm3, ymmword ptr [2*ebp - 1024]
+
+// CHECK: vp2intersectd k6, ymm3, ymmword ptr [ecx + 4064]
+// CHECK: encoding: [0x62,0xf2,0x67,0x28,0x68,0x71,0x7f]
+ vp2intersectd k6, ymm3, ymmword ptr [ecx + 4064]
+
+// CHECK: vp2intersectd k6, ymm3, dword ptr [edx - 512]{1to8}
+// CHECK: encoding: [0x62,0xf2,0x67,0x38,0x68,0x72,0x80]
+ vp2intersectd k6, ymm3, dword ptr [edx - 512]{1to8}
+
+// CHECK: vp2intersectd k6, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0x62,0xf2,0x67,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10]
+ vp2intersectd k6, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+
+// CHECK: vp2intersectd k6, xmm3, xmmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0x62,0xf2,0x67,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00]
+ vp2intersectd k6, xmm3, xmmword ptr [edi + 4*eax + 291]
+
+// CHECK: vp2intersectd k6, xmm3, dword ptr [eax]{1to4}
+// CHECK: encoding: [0x62,0xf2,0x67,0x18,0x68,0x30]
+ vp2intersectd k6, xmm3, dword ptr [eax]{1to4}
+
+// CHECK: vp2intersectd k6, xmm3, xmmword ptr [2*ebp - 512]
+// CHECK: encoding: [0x62,0xf2,0x67,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff]
+ vp2intersectd k6, xmm3, xmmword ptr [2*ebp - 512]
+
+// CHECK: vp2intersectd k6, xmm3, xmmword ptr [ecx + 2032]
+// CHECK: encoding: [0x62,0xf2,0x67,0x08,0x68,0x71,0x7f]
+ vp2intersectd k6, xmm3, xmmword ptr [ecx + 2032]
+
+// CHECK: vp2intersectd k6, xmm3, dword ptr [edx - 512]{1to4}
+// CHECK: encoding: [0x62,0xf2,0x67,0x18,0x68,0x72,0x80]
+ vp2intersectd k6, xmm3, dword ptr [edx - 512]{1to4}
+
+// CHECK: vp2intersectq k6, ymm3, ymm4
+// CHECK: encoding: [0x62,0xf2,0xe7,0x28,0x68,0xf4]
+ vp2intersectq k6, ymm3, ymm4
+
+// CHECK: vp2intersectq k6, xmm3, xmm4
+// CHECK: encoding: [0x62,0xf2,0xe7,0x08,0x68,0xf4]
+ vp2intersectq k6, xmm3, xmm4
+
+// CHECK: vp2intersectq k6, ymm3, ymmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0x62,0xf2,0xe7,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10]
+ vp2intersectq k6, ymm3, ymmword ptr [esp + 8*esi + 268435456]
+
+// CHECK: vp2intersectq k6, ymm3, ymmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0x62,0xf2,0xe7,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00]
+ vp2intersectq k6, ymm3, ymmword ptr [edi + 4*eax + 291]
+
+// CHECK: vp2intersectq k6, ymm3, qword ptr [eax]{1to4}
+// CHECK: encoding: [0x62,0xf2,0xe7,0x38,0x68,0x30]
+ vp2intersectq k6, ymm3, qword ptr [eax]{1to4}
+
+// CHECK: vp2intersectq k6, ymm3, ymmword ptr [2*ebp - 1024]
+// CHECK: encoding: [0x62,0xf2,0xe7,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff]
+ vp2intersectq k6, ymm3, ymmword ptr [2*ebp - 1024]
+
+// CHECK: vp2intersectq k6, ymm3, ymmword ptr [ecx + 4064]
+// CHECK: encoding: [0x62,0xf2,0xe7,0x28,0x68,0x71,0x7f]
+ vp2intersectq k6, ymm3, ymmword ptr [ecx + 4064]
+
+// CHECK: vp2intersectq k6, ymm3, qword ptr [edx - 1024]{1to4}
+// CHECK: encoding: [0x62,0xf2,0xe7,0x38,0x68,0x72,0x80]
+ vp2intersectq k6, ymm3, qword ptr [edx - 1024]{1to4}
+
+// CHECK: vp2intersectq k6, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0x62,0xf2,0xe7,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10]
+ vp2intersectq k6, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+
+// CHECK: vp2intersectq k6, xmm3, xmmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0x62,0xf2,0xe7,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00]
+ vp2intersectq k6, xmm3, xmmword ptr [edi + 4*eax + 291]
+
+// CHECK: vp2intersectq k6, xmm3, qword ptr [eax]{1to2}
+// CHECK: encoding: [0x62,0xf2,0xe7,0x18,0x68,0x30]
+ vp2intersectq k6, xmm3, qword ptr [eax]{1to2}
+
+// CHECK: vp2intersectq k6, xmm3, xmmword ptr [2*ebp - 512]
+// CHECK: encoding: [0x62,0xf2,0xe7,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff]
+ vp2intersectq k6, xmm3, xmmword ptr [2*ebp - 512]
+
+// CHECK: vp2intersectq k6, xmm3, xmmword ptr [ecx + 2032]
+// CHECK: encoding: [0x62,0xf2,0xe7,0x08,0x68,0x71,0x7f]
+ vp2intersectq k6, xmm3, xmmword ptr [ecx + 2032]
+
+// CHECK: vp2intersectq k6, xmm3, qword ptr [edx - 1024]{1to2}
+// CHECK: encoding: [0x62,0xf2,0xe7,0x18,0x68,0x72,0x80]
+ vp2intersectq k6, xmm3, qword ptr [edx - 1024]{1to2}
Added: llvm/trunk/test/MC/X86/x86-32-avx512_vp2intersect-intel.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-avx512_vp2intersect-intel.s?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32-avx512_vp2intersect-intel.s (added)
+++ llvm/trunk/test/MC/X86/x86-32-avx512_vp2intersect-intel.s Thu May 30 19:50:41 2019
@@ -0,0 +1,57 @@
+// RUN: llvm-mc -triple i386-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: vp2intersectd k4, zmm3, zmm4
+// CHECK: encoding: [0x62,0xf2,0x67,0x48,0x68,0xe4]
+ vp2intersectd k4, zmm3, zmm4
+
+// CHECK: vp2intersectd k4, zmm3, zmmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0x62,0xf2,0x67,0x48,0x68,0xa4,0xf4,0x00,0x00,0x00,0x10]
+ vp2intersectd k4, zmm3, zmmword ptr [esp + 8*esi + 268435456]
+
+// CHECK: vp2intersectd k4, zmm3, zmmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0x62,0xf2,0x67,0x48,0x68,0xa4,0x87,0x23,0x01,0x00,0x00]
+ vp2intersectd k4, zmm3, zmmword ptr [edi + 4*eax + 291]
+
+// CHECK: vp2intersectd k4, zmm3, dword ptr [eax]{1to16}
+// CHECK: encoding: [0x62,0xf2,0x67,0x58,0x68,0x20]
+ vp2intersectd k4, zmm3, dword ptr [eax]{1to16}
+
+// CHECK: vp2intersectd k4, zmm3, zmmword ptr [2*ebp - 2048]
+// CHECK: encoding: [0x62,0xf2,0x67,0x48,0x68,0x24,0x6d,0x00,0xf8,0xff,0xff]
+ vp2intersectd k4, zmm3, zmmword ptr [2*ebp - 2048]
+
+// CHECK: vp2intersectd k4, zmm3, zmmword ptr [ecx + 8128]
+// CHECK: encoding: [0x62,0xf2,0x67,0x48,0x68,0x61,0x7f]
+ vp2intersectd k4, zmm3, zmmword ptr [ecx + 8128]
+
+// CHECK: vp2intersectd k4, zmm3, dword ptr [edx - 512]{1to16}
+// CHECK: encoding: [0x62,0xf2,0x67,0x58,0x68,0x62,0x80]
+ vp2intersectd k4, zmm3, dword ptr [edx - 512]{1to16}
+
+// CHECK: vp2intersectq k4, zmm3, zmm4
+// CHECK: encoding: [0x62,0xf2,0xe7,0x48,0x68,0xe4]
+ vp2intersectq k4, zmm3, zmm4
+
+// CHECK: vp2intersectq k4, zmm3, zmmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0x62,0xf2,0xe7,0x48,0x68,0xa4,0xf4,0x00,0x00,0x00,0x10]
+ vp2intersectq k4, zmm3, zmmword ptr [esp + 8*esi + 268435456]
+
+// CHECK: vp2intersectq k4, zmm3, zmmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0x62,0xf2,0xe7,0x48,0x68,0xa4,0x87,0x23,0x01,0x00,0x00]
+ vp2intersectq k4, zmm3, zmmword ptr [edi + 4*eax + 291]
+
+// CHECK: vp2intersectq k4, zmm3, qword ptr [eax]{1to8}
+// CHECK: encoding: [0x62,0xf2,0xe7,0x58,0x68,0x20]
+ vp2intersectq k4, zmm3, qword ptr [eax]{1to8}
+
+// CHECK: vp2intersectq k4, zmm3, zmmword ptr [2*ebp - 2048]
+// CHECK: encoding: [0x62,0xf2,0xe7,0x48,0x68,0x24,0x6d,0x00,0xf8,0xff,0xff]
+ vp2intersectq k4, zmm3, zmmword ptr [2*ebp - 2048]
+
+// CHECK: vp2intersectq k4, zmm3, zmmword ptr [ecx + 8128]
+// CHECK: encoding: [0x62,0xf2,0xe7,0x48,0x68,0x61,0x7f]
+ vp2intersectq k4, zmm3, zmmword ptr [ecx + 8128]
+
+// CHECK: vp2intersectq k4, zmm3, qword ptr [edx - 1024]{1to8}
+// CHECK: encoding: [0x62,0xf2,0xe7,0x58,0x68,0x62,0x80]
+ vp2intersectq k4, zmm3, qword ptr [edx - 1024]{1to8}
+
Added: llvm/trunk/test/MC/X86/x86-32-avx512vp2intersect-att.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-avx512vp2intersect-att.s?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32-avx512vp2intersect-att.s (added)
+++ llvm/trunk/test/MC/X86/x86-32-avx512vp2intersect-att.s Thu May 30 19:50:41 2019
@@ -0,0 +1,225 @@
+// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK: vp2intersectq %zmm2, %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2]
+vp2intersectq %zmm2, %zmm1, %k0
+
+// CHECK: vp2intersectq (%edi), %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07]
+vp2intersectq (%edi), %zmm1, %k0
+
+// CHECK: vp2intersectq (%edi){1to8}, %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07]
+vp2intersectq (%edi){1to8}, %zmm1, %k0
+
+// CHECK: vp2intersectq %zmm2, %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2]
+vp2intersectq %zmm2, %zmm1, %k1
+
+// CHECK: vp2intersectq (%edi), %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07]
+vp2intersectq (%edi), %zmm1, %k1
+
+// CHECK: vp2intersectq (%edi){1to8}, %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07]
+vp2intersectq (%edi){1to8}, %zmm1, %k1
+
+// CHECK: vp2intersectq %zmm7, %zmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7]
+vp2intersectq %zmm7, %zmm4, %k6
+
+// CHECK: vp2intersectq (%esi), %zmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0x36]
+vp2intersectq (%esi), %zmm4, %k6
+
+// CHECK: vp2intersectq (%esi){1to8}, %zmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x58,0x68,0x36]
+vp2intersectq (%esi){1to8}, %zmm4, %k6
+
+// CHECK: vp2intersectq %zmm7, %zmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7]
+vp2intersectq %zmm7, %zmm4, %k7
+
+// CHECK: vp2intersectq (%esi), %zmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0x36]
+vp2intersectq (%esi), %zmm4, %k7
+
+// CHECK: vp2intersectq (%esi){1to8}, %zmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x58,0x68,0x36]
+vp2intersectq (%esi){1to8}, %zmm4, %k7
+
+// CHECK: vp2intersectq %ymm2, %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2]
+vp2intersectq %ymm2, %ymm1, %k0
+
+// CHECK: vp2intersectq (%edi), %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07]
+vp2intersectq (%edi), %ymm1, %k0
+
+// CHECK: vp2intersectq (%edi){1to4}, %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07]
+vp2intersectq (%edi){1to4}, %ymm1, %k0
+
+// CHECK: vp2intersectq %ymm2, %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2]
+vp2intersectq %ymm2, %ymm1, %k1
+
+// CHECK: vp2intersectq (%edi), %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07]
+vp2intersectq (%edi), %ymm1, %k1
+
+// CHECK: vp2intersectq (%edi){1to4}, %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07]
+vp2intersectq (%edi){1to4}, %ymm1, %k1
+
+// CHECK: vp2intersectq %ymm7, %ymm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0xf7]
+vp2intersectq %ymm7, %ymm4, %k6
+
+// CHECK: vp2intersectq (%esi), %ymm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0x36]
+vp2intersectq (%esi), %ymm4, %k6
+
+// CHECK: vp2intersectq (%esi){1to4}, %ymm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x38,0x68,0x36]
+vp2intersectq (%esi){1to4}, %ymm4, %k6
+
+// CHECK: vp2intersectq %ymm7, %ymm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0xf7]
+vp2intersectq %ymm7, %ymm4, %k7
+
+// CHECK: vp2intersectq (%esi), %ymm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0x36]
+vp2intersectq (%esi), %ymm4, %k7
+
+// CHECK: vp2intersectq %xmm2, %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2]
+vp2intersectq %xmm2, %xmm1, %k0
+
+// CHECK: vp2intersectq (%edi), %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07]
+vp2intersectq (%edi), %xmm1, %k0
+
+// CHECK: vp2intersectq (%edi){1to2}, %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x18,0x68,0x07]
+vp2intersectq (%edi){1to2}, %xmm1, %k0
+
+// CHECK: vp2intersectq %xmm2, %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2]
+vp2intersectq %xmm2, %xmm1, %k1
+
+// CHECK: vp2intersectq (%edi), %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07]
+vp2intersectq (%edi), %xmm1, %k1
+
+// CHECK: vp2intersectq %xmm7, %xmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0xf7]
+vp2intersectq %xmm7, %xmm4, %k6
+
+// CHECK: vp2intersectq (%esi), %xmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0x36]
+vp2intersectq (%esi), %xmm4, %k6
+
+// CHECK: vp2intersectq %xmm7, %xmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0xf7]
+vp2intersectq %xmm7, %xmm4, %k7
+
+// CHECK: vp2intersectq (%esi), %xmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0x36]
+vp2intersectq (%esi), %xmm4, %k7
+
+// CHECK: vp2intersectd %zmm2, %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2]
+vp2intersectd %zmm2, %zmm1, %k0
+
+// CHECK: vp2intersectd (%edi), %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07]
+vp2intersectd (%edi), %zmm1, %k0
+
+// CHECK: vp2intersectd %zmm2, %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2]
+vp2intersectd %zmm2, %zmm1, %k1
+
+// CHECK: vp2intersectd (%edi), %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07]
+vp2intersectd (%edi), %zmm1, %k1
+
+// CHECK: vp2intersectd %zmm7, %zmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0xf7]
+vp2intersectd %zmm7, %zmm4, %k6
+
+// CHECK: vp2intersectd (%esi), %zmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0x36]
+vp2intersectd (%esi), %zmm4, %k6
+
+// CHECK: vp2intersectd %zmm7, %zmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0xf7]
+vp2intersectd %zmm7, %zmm4, %k7
+
+// CHECK: vp2intersectd (%esi), %zmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0x36]
+vp2intersectd (%esi), %zmm4, %k7
+
+// CHECK: vp2intersectd %ymm2, %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2]
+vp2intersectd %ymm2, %ymm1, %k0
+
+// CHECK: vp2intersectd (%edi), %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07]
+vp2intersectd (%edi), %ymm1, %k0
+
+// CHECK: vp2intersectd %ymm2, %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2]
+vp2intersectd %ymm2, %ymm1, %k1
+
+// CHECK: vp2intersectd (%edi), %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07]
+vp2intersectd (%edi), %ymm1, %k1
+
+// CHECK: vp2intersectd %ymm7, %ymm4, %k6
+// CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0xf7]
+vp2intersectd %ymm7, %ymm4, %k6
+
+// CHECK: vp2intersectd (%esi), %ymm4, %k6
+// CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0x36]
+vp2intersectd (%esi), %ymm4, %k6
+
+// CHECK: vp2intersectd %ymm7, %ymm4, %k6
+// CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0xf7]
+vp2intersectd %ymm7, %ymm4, %k7
+
+// CHECK: vp2intersectd (%esi), %ymm4, %k6
+// CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0x36]
+vp2intersectd (%esi), %ymm4, %k7
+
+// CHECK: vp2intersectd %xmm2, %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2]
+vp2intersectd %xmm2, %xmm1, %k0
+
+// CHECK: vp2intersectd (%edi), %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07]
+vp2intersectd (%edi), %xmm1, %k0
+
+// CHECK: vp2intersectd %xmm2, %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2]
+vp2intersectd %xmm2, %xmm1, %k1
+
+// CHECK: vp2intersectd (%edi), %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07]
+vp2intersectd (%edi), %xmm1, %k1
+
+// CHECK: vp2intersectd %xmm7, %xmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0xf7]
+vp2intersectd %xmm7, %xmm4, %k6
+
+// CHECK: vp2intersectd (%esi), %xmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0x36]
+vp2intersectd (%esi), %xmm4, %k6
+
+// CHECK: vp2intersectd %xmm7, %xmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0xf7]
+vp2intersectd %xmm7, %xmm4, %k7
+
+// CHECK: vp2intersectd (%esi), %xmm4, %k6
+// CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0x36]
+vp2intersectd (%esi), %xmm4, %k7
Added: llvm/trunk/test/MC/X86/x86-64-avx512_vp2intersect-intel.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64-avx512_vp2intersect-intel.s?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64-avx512_vp2intersect-intel.s (added)
+++ llvm/trunk/test/MC/X86/x86-64-avx512_vp2intersect-intel.s Thu May 30 19:50:41 2019
@@ -0,0 +1,57 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: vp2intersectd k4, zmm23, zmm24
+// CHECK: encoding: [0x62,0x92,0x47,0x40,0x68,0xe0]
+ vp2intersectd k4, zmm23, zmm24
+
+// CHECK: vp2intersectd k4, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0x62,0xb2,0x47,0x40,0x68,0xa4,0xf5,0x00,0x00,0x00,0x10]
+ vp2intersectd k4, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vp2intersectd k4, zmm23, zmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0x62,0xd2,0x47,0x40,0x68,0xa4,0x80,0x23,0x01,0x00,0x00]
+ vp2intersectd k4, zmm23, zmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vp2intersectd k4, zmm23, dword ptr [rip]{1to16}
+// CHECK: encoding: [0x62,0xf2,0x47,0x50,0x68,0x25,0x00,0x00,0x00,0x00]
+ vp2intersectd k4, zmm23, dword ptr [rip]{1to16}
+
+// CHECK: vp2intersectd k4, zmm23, zmmword ptr [2*rbp - 2048]
+// CHECK: encoding: [0x62,0xf2,0x47,0x40,0x68,0x24,0x6d,0x00,0xf8,0xff,0xff]
+ vp2intersectd k4, zmm23, zmmword ptr [2*rbp - 2048]
+
+// CHECK: vp2intersectd k4, zmm23, zmmword ptr [rcx + 8128]
+// CHECK: encoding: [0x62,0xf2,0x47,0x40,0x68,0x61,0x7f]
+ vp2intersectd k4, zmm23, zmmword ptr [rcx + 8128]
+
+// CHECK: vp2intersectd k4, zmm23, dword ptr [rdx - 512]{1to16}
+// CHECK: encoding: [0x62,0xf2,0x47,0x50,0x68,0x62,0x80]
+ vp2intersectd k4, zmm23, dword ptr [rdx - 512]{1to16}
+
+// CHECK: vp2intersectq k4, zmm23, zmm24
+// CHECK: encoding: [0x62,0x92,0xc7,0x40,0x68,0xe0]
+ vp2intersectq k4, zmm23, zmm24
+
+// CHECK: vp2intersectq k4, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0x62,0xb2,0xc7,0x40,0x68,0xa4,0xf5,0x00,0x00,0x00,0x10]
+ vp2intersectq k4, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vp2intersectq k4, zmm23, zmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0x62,0xd2,0xc7,0x40,0x68,0xa4,0x80,0x23,0x01,0x00,0x00]
+ vp2intersectq k4, zmm23, zmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vp2intersectq k4, zmm23, qword ptr [rip]{1to8}
+// CHECK: encoding: [0x62,0xf2,0xc7,0x50,0x68,0x25,0x00,0x00,0x00,0x00]
+ vp2intersectq k4, zmm23, qword ptr [rip]{1to8}
+
+// CHECK: vp2intersectq k4, zmm23, zmmword ptr [2*rbp - 2048]
+// CHECK: encoding: [0x62,0xf2,0xc7,0x40,0x68,0x24,0x6d,0x00,0xf8,0xff,0xff]
+ vp2intersectq k4, zmm23, zmmword ptr [2*rbp - 2048]
+
+// CHECK: vp2intersectq k4, zmm23, zmmword ptr [rcx + 8128]
+// CHECK: encoding: [0x62,0xf2,0xc7,0x40,0x68,0x61,0x7f]
+ vp2intersectq k4, zmm23, zmmword ptr [rcx + 8128]
+
+// CHECK: vp2intersectq k4, zmm23, qword ptr [rdx - 1024]{1to8}
+// CHECK: encoding: [0x62,0xf2,0xc7,0x50,0x68,0x62,0x80]
+ vp2intersectq k4, zmm23, qword ptr [rdx - 1024]{1to8}
+
Added: llvm/trunk/test/MC/X86/x86-64-avx512vp2intersect-att.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64-avx512vp2intersect-att.s?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64-avx512vp2intersect-att.s (added)
+++ llvm/trunk/test/MC/X86/x86-64-avx512vp2intersect-att.s Thu May 30 19:50:41 2019
@@ -0,0 +1,231 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
+
+// v8i64 vectors
+// CHECK: vp2intersectq %zmm2, %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2]
+vp2intersectq %zmm2, %zmm1, %k0
+
+// CHECK: vp2intersectq (%rdi), %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07]
+vp2intersectq (%rdi), %zmm1, %k0
+
+// CHECK: vp2intersectq (%rdi){1to8}, %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07]
+vp2intersectq (%rdi){1to8}, %zmm1, %k0
+
+// CHECK: vp2intersectq %zmm2, %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2]
+vp2intersectq %zmm2, %zmm1, %k1
+
+// CHECK: vp2intersectq (%rdi), %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07]
+vp2intersectq (%rdi), %zmm1, %k1
+
+// CHECK: vp2intersectq (%rdi){1to8}, %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07]
+vp2intersectq (%rdi){1to8}, %zmm1, %k1
+
+// CHECK: vp2intersectq %zmm7, %zmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0xf7]
+vp2intersectq %zmm7, %zmm9, %k6
+
+// CHECK: vp2intersectq (%rsi), %zmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0x36]
+vp2intersectq (%rsi), %zmm9, %k6
+
+// CHECK: vp2intersectq (%rsi){1to8}, %zmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x58,0x68,0x36]
+vp2intersectq (%rsi){1to8}, %zmm9, %k6
+
+// CHECK: vp2intersectq %zmm7, %zmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0xf7]
+vp2intersectq %zmm7, %zmm9, %k7
+
+// CHECK: vp2intersectq (%rsi), %zmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0x36]
+vp2intersectq (%rsi), %zmm9, %k7
+
+// CHECK: vp2intersectq (%rsi){1to8}, %zmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x58,0x68,0x36]
+vp2intersectq (%rsi){1to8}, %zmm9, %k7
+
+// v4i64 vectors
+// CHECK: vp2intersectq %ymm2, %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2]
+vp2intersectq %ymm2, %ymm1, %k0
+
+// CHECK: vp2intersectq (%rdi), %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07]
+vp2intersectq (%rdi), %ymm1, %k0
+
+// CHECK: vp2intersectq (%rdi){1to4}, %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07]
+vp2intersectq (%rdi){1to4}, %ymm1, %k0
+
+// CHECK: vp2intersectq %ymm2, %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2]
+vp2intersectq %ymm2, %ymm1, %k1
+
+// CHECK: vp2intersectq (%rdi), %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07]
+vp2intersectq (%rdi), %ymm1, %k1
+
+// CHECK: vp2intersectq (%rdi){1to4}, %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07]
+vp2intersectq (%rdi){1to4}, %ymm1, %k1
+
+// CHECK: vp2intersectq %ymm7, %ymm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0xf7]
+vp2intersectq %ymm7, %ymm9, %k6
+
+// CHECK: vp2intersectq (%rsi), %ymm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0x36]
+vp2intersectq (%rsi), %ymm9, %k6
+
+// CHECK: vp2intersectq (%rsi){1to4}, %ymm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x38,0x68,0x36]
+vp2intersectq (%rsi){1to4}, %ymm9, %k6
+
+// CHECK: vp2intersectq %ymm7, %ymm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0xf7]
+vp2intersectq %ymm7, %ymm9, %k7
+
+// CHECK: vp2intersectq (%rsi), %ymm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0x36]
+vp2intersectq (%rsi), %ymm9, %k7
+
+// v2i64 vectors
+// CHECK: vp2intersectq %xmm2, %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2]
+vp2intersectq %xmm2, %xmm1, %k0
+
+// CHECK: vp2intersectq (%rdi), %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07]
+vp2intersectq (%rdi), %xmm1, %k0
+
+// CHECK: vp2intersectq (%rdi){1to2}, %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x18,0x68,0x07]
+vp2intersectq (%rdi){1to2}, %xmm1, %k0
+
+// CHECK: vp2intersectq %xmm2, %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2]
+vp2intersectq %xmm2, %xmm1, %k1
+
+// CHECK: vp2intersectq (%rdi), %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07]
+vp2intersectq (%rdi), %xmm1, %k1
+
+// CHECK: vp2intersectq %xmm7, %xmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0xf7]
+vp2intersectq %xmm7, %xmm9, %k6
+
+// CHECK: vp2intersectq (%rsi), %xmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0x36]
+vp2intersectq (%rsi), %xmm9, %k6
+
+// CHECK: vp2intersectq %xmm7, %xmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0xf7]
+vp2intersectq %xmm7, %xmm9, %k7
+
+// CHECK: vp2intersectq (%rsi), %xmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0x36]
+vp2intersectq (%rsi), %xmm9, %k7
+
+// v16i32 vectors
+// CHECK: vp2intersectd %zmm2, %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2]
+vp2intersectd %zmm2, %zmm1, %k0
+
+// CHECK: vp2intersectd (%rdi), %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07]
+vp2intersectd (%rdi), %zmm1, %k0
+
+// CHECK: vp2intersectd %zmm2, %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2]
+vp2intersectd %zmm2, %zmm1, %k1
+
+// CHECK: vp2intersectd (%rdi), %zmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07]
+vp2intersectd (%rdi), %zmm1, %k1
+
+// CHECK: vp2intersectd %zmm7, %zmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0xf7]
+vp2intersectd %zmm7, %zmm9, %k6
+
+// CHECK: vp2intersectd (%rsi), %zmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0x36]
+vp2intersectd (%rsi), %zmm9, %k6
+
+// CHECK: vp2intersectd %zmm7, %zmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0xf7]
+vp2intersectd %zmm7, %zmm9, %k7
+
+// CHECK: vp2intersectd (%rsi), %zmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0x36]
+vp2intersectd (%rsi), %zmm9, %k7
+
+// v8i32 vectors
+// CHECK: vp2intersectd %ymm2, %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2]
+vp2intersectd %ymm2, %ymm1, %k0
+
+// CHECK: vp2intersectd (%rdi), %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07]
+vp2intersectd (%rdi), %ymm1, %k0
+
+// CHECK: vp2intersectd %ymm2, %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2]
+vp2intersectd %ymm2, %ymm1, %k1
+
+// CHECK: vp2intersectd (%rdi), %ymm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07]
+vp2intersectd (%rdi), %ymm1, %k1
+
+// CHECK: vp2intersectd %ymm7, %ymm9, %k6
+// CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0xf7]
+vp2intersectd %ymm7, %ymm9, %k6
+
+// CHECK: vp2intersectd (%rsi), %ymm9, %k6
+// CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0x36]
+vp2intersectd (%rsi), %ymm9, %k6
+
+// CHECK: vp2intersectd %ymm7, %ymm9, %k6
+// CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0xf7]
+vp2intersectd %ymm7, %ymm9, %k7
+
+// CHECK: vp2intersectd (%rsi), %ymm9, %k6
+// CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0x36]
+vp2intersectd (%rsi), %ymm9, %k7
+
+// v4i32 vectors
+// CHECK: vp2intersectd %xmm2, %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2]
+vp2intersectd %xmm2, %xmm1, %k0
+
+// CHECK: vp2intersectd (%rdi), %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07]
+vp2intersectd (%rdi), %xmm1, %k0
+
+// CHECK: vp2intersectd %xmm2, %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2]
+vp2intersectd %xmm2, %xmm1, %k1
+
+// CHECK: vp2intersectd (%rdi), %xmm1, %k0
+// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07]
+vp2intersectd (%rdi), %xmm1, %k1
+
+// CHECK: vp2intersectd %xmm7, %xmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0xf7]
+vp2intersectd %xmm7, %xmm9, %k6
+
+// CHECK: vp2intersectd (%rsi), %xmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0x36]
+vp2intersectd (%rsi), %xmm9, %k6
+
+// CHECK: vp2intersectd %xmm7, %xmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0xf7]
+vp2intersectd %xmm7, %xmm9, %k7
+
+// CHECK: vp2intersectd (%rsi), %xmm9, %k6
+// CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0x36]
+vp2intersectd (%rsi), %xmm9, %k7
Added: llvm/trunk/test/MC/X86/x86-64-avx512vp2intersectvl-att.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64-avx512vp2intersectvl-att.s?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64-avx512vp2intersectvl-att.s (added)
+++ llvm/trunk/test/MC/X86/x86-64-avx512vp2intersectvl-att.s Thu May 30 19:50:41 2019
@@ -0,0 +1,113 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding < %s | FileCheck %s
+
+// CHECK: vp2intersectd %ymm24, %ymm23, %k6
+// CHECK: encoding: [0x62,0x92,0x47,0x20,0x68,0xf0]
+ vp2intersectd %ymm24, %ymm23, %k6
+
+// CHECK: vp2intersectd %xmm24, %xmm23, %k6
+// CHECK: encoding: [0x62,0x92,0x47,0x00,0x68,0xf0]
+ vp2intersectd %xmm24, %xmm23, %k6
+
+// CHECK: vp2intersectd 268435456(%rbp,%r14,8), %ymm23, %k6
+// CHECK: encoding: [0x62,0xb2,0x47,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10]
+ vp2intersectd 268435456(%rbp,%r14,8), %ymm23, %k6
+
+// CHECK: vp2intersectd 291(%r8,%rax,4), %ymm23, %k6
+// CHECK: encoding: [0x62,0xd2,0x47,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00]
+ vp2intersectd 291(%r8,%rax,4), %ymm23, %k6
+
+// CHECK: vp2intersectd (%rip){1to8}, %ymm23, %k6
+// CHECK: encoding: [0x62,0xf2,0x47,0x30,0x68,0x35,0x00,0x00,0x00,0x00]
+ vp2intersectd (%rip){1to8}, %ymm23, %k6
+
+// CHECK: vp2intersectd -1024(,%rbp,2), %ymm23, %k6
+// CHECK: encoding: [0x62,0xf2,0x47,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff]
+ vp2intersectd -1024(,%rbp,2), %ymm23, %k6
+
+// CHECK: vp2intersectd 4064(%rcx), %ymm23, %k6
+// CHECK: encoding: [0x62,0xf2,0x47,0x20,0x68,0x71,0x7f]
+ vp2intersectd 4064(%rcx), %ymm23, %k6
+
+// CHECK: vp2intersectd -512(%rdx){1to8}, %ymm23, %k6
+// CHECK: encoding: [0x62,0xf2,0x47,0x30,0x68,0x72,0x80]
+ vp2intersectd -512(%rdx){1to8}, %ymm23, %k6
+
+// CHECK: vp2intersectd 268435456(%rbp,%r14,8), %xmm23, %k6
+// CHECK: encoding: [0x62,0xb2,0x47,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10]
+ vp2intersectd 268435456(%rbp,%r14,8), %xmm23, %k6
+
+// CHECK: vp2intersectd 291(%r8,%rax,4), %xmm23, %k6
+// CHECK: encoding: [0x62,0xd2,0x47,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00]
+ vp2intersectd 291(%r8,%rax,4), %xmm23, %k6
+
+// CHECK: vp2intersectd (%rip){1to4}, %xmm23, %k6
+// CHECK: encoding: [0x62,0xf2,0x47,0x10,0x68,0x35,0x00,0x00,0x00,0x00]
+ vp2intersectd (%rip){1to4}, %xmm23, %k6
+
+// CHECK: vp2intersectd -512(,%rbp,2), %xmm23, %k6
+// CHECK: encoding: [0x62,0xf2,0x47,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff]
+ vp2intersectd -512(,%rbp,2), %xmm23, %k6
+
+// CHECK: vp2intersectd 2032(%rcx), %xmm23, %k6
+// CHECK: encoding: [0x62,0xf2,0x47,0x00,0x68,0x71,0x7f]
+ vp2intersectd 2032(%rcx), %xmm23, %k6
+
+// CHECK: vp2intersectd -512(%rdx){1to4}, %xmm23, %k6
+// CHECK: encoding: [0x62,0xf2,0x47,0x10,0x68,0x72,0x80]
+ vp2intersectd -512(%rdx){1to4}, %xmm23, %k6
+
+// CHECK: vp2intersectq %ymm24, %ymm23, %k6
+// CHECK: encoding: [0x62,0x92,0xc7,0x20,0x68,0xf0]
+ vp2intersectq %ymm24, %ymm23, %k6
+
+// CHECK: vp2intersectq %xmm24, %xmm23, %k6
+// CHECK: encoding: [0x62,0x92,0xc7,0x00,0x68,0xf0]
+ vp2intersectq %xmm24, %xmm23, %k6
+
+// CHECK: vp2intersectq 268435456(%rbp,%r14,8), %ymm23, %k6
+// CHECK: encoding: [0x62,0xb2,0xc7,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10]
+ vp2intersectq 268435456(%rbp,%r14,8), %ymm23, %k6
+
+// CHECK: vp2intersectq 291(%r8,%rax,4), %ymm23, %k6
+// CHECK: encoding: [0x62,0xd2,0xc7,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00]
+ vp2intersectq 291(%r8,%rax,4), %ymm23, %k6
+
+// CHECK: vp2intersectq (%rip){1to4}, %ymm23, %k6
+// CHECK: encoding: [0x62,0xf2,0xc7,0x30,0x68,0x35,0x00,0x00,0x00,0x00]
+ vp2intersectq (%rip){1to4}, %ymm23, %k6
+
+// CHECK: vp2intersectq -1024(,%rbp,2), %ymm23, %k6
+// CHECK: encoding: [0x62,0xf2,0xc7,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff]
+ vp2intersectq -1024(,%rbp,2), %ymm23, %k6
+
+// CHECK: vp2intersectq 4064(%rcx), %ymm23, %k6
+// CHECK: encoding: [0x62,0xf2,0xc7,0x20,0x68,0x71,0x7f]
+ vp2intersectq 4064(%rcx), %ymm23, %k6
+
+// CHECK: vp2intersectq -1024(%rdx){1to4}, %ymm23, %k6
+// CHECK: encoding: [0x62,0xf2,0xc7,0x30,0x68,0x72,0x80]
+ vp2intersectq -1024(%rdx){1to4}, %ymm23, %k6
+
+// CHECK: vp2intersectq 268435456(%rbp,%r14,8), %xmm23, %k6
+// CHECK: encoding: [0x62,0xb2,0xc7,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10]
+ vp2intersectq 268435456(%rbp,%r14,8), %xmm23, %k6
+
+// CHECK: vp2intersectq 291(%r8,%rax,4), %xmm23, %k6
+// CHECK: encoding: [0x62,0xd2,0xc7,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00]
+ vp2intersectq 291(%r8,%rax,4), %xmm23, %k6
+
+// CHECK: vp2intersectq (%rip){1to2}, %xmm23, %k6
+// CHECK: encoding: [0x62,0xf2,0xc7,0x10,0x68,0x35,0x00,0x00,0x00,0x00]
+ vp2intersectq (%rip){1to2}, %xmm23, %k6
+
+// CHECK: vp2intersectq -512(,%rbp,2), %xmm23, %k6
+// CHECK: encoding: [0x62,0xf2,0xc7,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff]
+ vp2intersectq -512(,%rbp,2), %xmm23, %k6
+
+// CHECK: vp2intersectq 2032(%rcx), %xmm23, %k6
+// CHECK: encoding: [0x62,0xf2,0xc7,0x00,0x68,0x71,0x7f]
+ vp2intersectq 2032(%rcx), %xmm23, %k6
+
+// CHECK: vp2intersectq -1024(%rdx){1to2}, %xmm23, %k6
+// CHECK: encoding: [0x62,0xf2,0xc7,0x10,0x68,0x72,0x80]
+ vp2intersectq -1024(%rdx){1to2}, %xmm23, %k6
Added: llvm/trunk/test/MC/X86/x86-64-avx512vp2intersectvl-intel.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64-avx512vp2intersectvl-intel.s?rev=362188&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64-avx512vp2intersectvl-intel.s (added)
+++ llvm/trunk/test/MC/X86/x86-64-avx512vp2intersectvl-intel.s Thu May 30 19:50:41 2019
@@ -0,0 +1,113 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vp2intersectd k6, ymm23, ymm24
+// CHECK: encoding: [0x62,0x92,0x47,0x20,0x68,0xf0]
+ vp2intersectd k6, ymm23, ymm24
+
+// CHECK: vp2intersectd k6, xmm23, xmm24
+// CHECK: encoding: [0x62,0x92,0x47,0x00,0x68,0xf0]
+ vp2intersectd k6, xmm23, xmm24
+
+// CHECK: vp2intersectd k6, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0x62,0xb2,0x47,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10]
+ vp2intersectd k6, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vp2intersectd k6, ymm23, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0x62,0xd2,0x47,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00]
+ vp2intersectd k6, ymm23, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vp2intersectd k6, ymm23, dword ptr [rip]{1to8}
+// CHECK: encoding: [0x62,0xf2,0x47,0x30,0x68,0x35,0x00,0x00,0x00,0x00]
+ vp2intersectd k6, ymm23, dword ptr [rip]{1to8}
+
+// CHECK: vp2intersectd k6, ymm23, ymmword ptr [2*rbp - 1024]
+// CHECK: encoding: [0x62,0xf2,0x47,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff]
+ vp2intersectd k6, ymm23, ymmword ptr [2*rbp - 1024]
+
+// CHECK: vp2intersectd k6, ymm23, ymmword ptr [rcx + 4064]
+// CHECK: encoding: [0x62,0xf2,0x47,0x20,0x68,0x71,0x7f]
+ vp2intersectd k6, ymm23, ymmword ptr [rcx + 4064]
+
+// CHECK: vp2intersectd k6, ymm23, dword ptr [rdx - 512]{1to8}
+// CHECK: encoding: [0x62,0xf2,0x47,0x30,0x68,0x72,0x80]
+ vp2intersectd k6, ymm23, dword ptr [rdx - 512]{1to8}
+
+// CHECK: vp2intersectd k6, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0x62,0xb2,0x47,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10]
+ vp2intersectd k6, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vp2intersectd k6, xmm23, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0x62,0xd2,0x47,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00]
+ vp2intersectd k6, xmm23, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vp2intersectd k6, xmm23, dword ptr [rip]{1to4}
+// CHECK: encoding: [0x62,0xf2,0x47,0x10,0x68,0x35,0x00,0x00,0x00,0x00]
+ vp2intersectd k6, xmm23, dword ptr [rip]{1to4}
+
+// CHECK: vp2intersectd k6, xmm23, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0x62,0xf2,0x47,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff]
+ vp2intersectd k6, xmm23, xmmword ptr [2*rbp - 512]
+
+// CHECK: vp2intersectd k6, xmm23, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0x62,0xf2,0x47,0x00,0x68,0x71,0x7f]
+ vp2intersectd k6, xmm23, xmmword ptr [rcx + 2032]
+
+// CHECK: vp2intersectd k6, xmm23, dword ptr [rdx - 512]{1to4}
+// CHECK: encoding: [0x62,0xf2,0x47,0x10,0x68,0x72,0x80]
+ vp2intersectd k6, xmm23, dword ptr [rdx - 512]{1to4}
+
+// CHECK: vp2intersectq k6, ymm23, ymm24
+// CHECK: encoding: [0x62,0x92,0xc7,0x20,0x68,0xf0]
+ vp2intersectq k6, ymm23, ymm24
+
+// CHECK: vp2intersectq k6, xmm23, xmm24
+// CHECK: encoding: [0x62,0x92,0xc7,0x00,0x68,0xf0]
+ vp2intersectq k6, xmm23, xmm24
+
+// CHECK: vp2intersectq k6, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0x62,0xb2,0xc7,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10]
+ vp2intersectq k6, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vp2intersectq k6, ymm23, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0x62,0xd2,0xc7,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00]
+ vp2intersectq k6, ymm23, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vp2intersectq k6, ymm23, qword ptr [rip]{1to4}
+// CHECK: encoding: [0x62,0xf2,0xc7,0x30,0x68,0x35,0x00,0x00,0x00,0x00]
+ vp2intersectq k6, ymm23, qword ptr [rip]{1to4}
+
+// CHECK: vp2intersectq k6, ymm23, ymmword ptr [2*rbp - 1024]
+// CHECK: encoding: [0x62,0xf2,0xc7,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff]
+ vp2intersectq k6, ymm23, ymmword ptr [2*rbp - 1024]
+
+// CHECK: vp2intersectq k6, ymm23, ymmword ptr [rcx + 4064]
+// CHECK: encoding: [0x62,0xf2,0xc7,0x20,0x68,0x71,0x7f]
+ vp2intersectq k6, ymm23, ymmword ptr [rcx + 4064]
+
+// CHECK: vp2intersectq k6, ymm23, qword ptr [rdx - 1024]{1to4}
+// CHECK: encoding: [0x62,0xf2,0xc7,0x30,0x68,0x72,0x80]
+ vp2intersectq k6, ymm23, qword ptr [rdx - 1024]{1to4}
+
+// CHECK: vp2intersectq k6, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0x62,0xb2,0xc7,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10]
+ vp2intersectq k6, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vp2intersectq k6, xmm23, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0x62,0xd2,0xc7,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00]
+ vp2intersectq k6, xmm23, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vp2intersectq k6, xmm23, qword ptr [rip]{1to2}
+// CHECK: encoding: [0x62,0xf2,0xc7,0x10,0x68,0x35,0x00,0x00,0x00,0x00]
+ vp2intersectq k6, xmm23, qword ptr [rip]{1to2}
+
+// CHECK: vp2intersectq k6, xmm23, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0x62,0xf2,0xc7,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff]
+ vp2intersectq k6, xmm23, xmmword ptr [2*rbp - 512]
+
+// CHECK: vp2intersectq k6, xmm23, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0x62,0xf2,0xc7,0x00,0x68,0x71,0x7f]
+ vp2intersectq k6, xmm23, xmmword ptr [rcx + 2032]
+
+// CHECK: vp2intersectq k6, xmm23, qword ptr [rdx - 1024]{1to2}
+// CHECK: encoding: [0x62,0xf2,0xc7,0x10,0x68,0x72,0x80]
+ vp2intersectq k6, xmm23, qword ptr [rdx - 1024]{1to2}
Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=362188&r1=362187&r2=362188&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Thu May 30 19:50:41 2019
@@ -932,6 +932,11 @@ OperandType RecognizableInstr::typeFromS
TYPE("VK32WM", TYPE_VK)
TYPE("VK64", TYPE_VK)
TYPE("VK64WM", TYPE_VK)
+ TYPE("VK1Pair", TYPE_VK_PAIR)
+ TYPE("VK2Pair", TYPE_VK_PAIR)
+ TYPE("VK4Pair", TYPE_VK_PAIR)
+ TYPE("VK8Pair", TYPE_VK_PAIR)
+ TYPE("VK16Pair", TYPE_VK_PAIR)
TYPE("vx64mem", TYPE_MVSIBX)
TYPE("vx128mem", TYPE_MVSIBX)
TYPE("vx256mem", TYPE_MVSIBX)
@@ -1016,6 +1021,11 @@ RecognizableInstr::rmRegisterEncodingFro
ENCODING("VK16", ENCODING_RM)
ENCODING("VK32", ENCODING_RM)
ENCODING("VK64", ENCODING_RM)
+ ENCODING("VK1PAIR", ENCODING_RM)
+ ENCODING("VK2PAIR", ENCODING_RM)
+ ENCODING("VK4PAIR", ENCODING_RM)
+ ENCODING("VK8PAIR", ENCODING_RM)
+ ENCODING("VK16PAIR", ENCODING_RM)
ENCODING("BNDR", ENCODING_RM)
errs() << "Unhandled R/M register encoding " << s << "\n";
llvm_unreachable("Unhandled R/M register encoding");
@@ -1050,6 +1060,11 @@ RecognizableInstr::roRegisterEncodingFro
ENCODING("VK16", ENCODING_REG)
ENCODING("VK32", ENCODING_REG)
ENCODING("VK64", ENCODING_REG)
+ ENCODING("VK1Pair", ENCODING_REG)
+ ENCODING("VK2Pair", ENCODING_REG)
+ ENCODING("VK4Pair", ENCODING_REG)
+ ENCODING("VK8Pair", ENCODING_REG)
+ ENCODING("VK16Pair", ENCODING_REG)
ENCODING("VK1WM", ENCODING_REG)
ENCODING("VK2WM", ENCODING_REG)
ENCODING("VK4WM", ENCODING_REG)
@@ -1084,6 +1099,11 @@ RecognizableInstr::vvvvRegisterEncodingF
ENCODING("VK16", ENCODING_VVVV)
ENCODING("VK32", ENCODING_VVVV)
ENCODING("VK64", ENCODING_VVVV)
+ ENCODING("VK1PAIR", ENCODING_VVVV)
+ ENCODING("VK2PAIR", ENCODING_VVVV)
+ ENCODING("VK4PAIR", ENCODING_VVVV)
+ ENCODING("VK8PAIR", ENCODING_VVVV)
+ ENCODING("VK16PAIR", ENCODING_VVVV)
errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
llvm_unreachable("Unhandled VEX.vvvv register encoding");
}
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