[PATCH] D62673: [ARM] Add MVE vector bit-operations (register inputs).

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham created this revision.
simon_tatham added reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

This includes all the obvious bitwise operations (AND, OR, BIC, ORN,
MVN); byte-order reverse instructions; and the VMOVs that access a
single lane of a vector.

Some of those VMOVs (specifically, the ones that access a 32-bit lane)
share an encoding with existing instructions that were disassembled as
accessing half of a d-register (e.g. `vmov.32 r0, d1[0]`), but in
8.1-M they're now written as accessing a quarter of a q-register (e.g.
`vmov.32 r0, q0[2]`). The older syntax is still accepted by the
assembler.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D62673

Files:
  llvm/lib/Target/ARM/ARMInstrFormats.td
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
  llvm/test/MC/ARM/mve-bitops.s
  llvm/test/MC/ARM/mve-vmov-lane.s
  llvm/test/MC/Disassembler/ARM/mve-bitops.txt
  llvm/test/MC/Disassembler/ARM/mve-vmov-lane.txt

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