[PATCH] D62608: [ARM64, COFF] Add CodeView register mapping

Wed May 29 14:33:41 PDT 2019

rnk added a comment.

In D62608#1521945 <https://reviews.llvm.org/D62608#1521945>, @efriedma wrote:

> The code looks fine now.  I'm okay with putting off fixes for dumping code that incorrectly assumes x86.

The dumping tools are the foundation of our testing strategy, so I think we should take the time to fix them early on. It should be a matter of changing `getRegisterNames` to accept a CPU type, switch, and return the appropriate (x86 or arm) enum table, maybe just returning x86 by default to preserve existing behavior. Both symbol dumpers already store the compilation CPU type from the S_COMPILE3 record, so this shouldn't be too complicated.

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Comment at: test/DebugInfo/COFF/register-variables-arm64.ll:26
+; OBJ:     Kind: S_DEFRANGE_REGISTER_REL (0x1145)
+; OBJ:     BaseRegister: {{.*}} (0x51)
+; OBJ:     HasSpilledUDTMember: No
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So, you have to wild card the register here because the dumper assumes x86 registers. I think we should take the time to fix that now before we accumulate more tests.

Repository:
  rL LLVM

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https://reviews.llvm.org/D62608