[llvm] r361935 - [AArch64][SVE2] Asm: support Floating Point Widening Multiply-Add
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Wed May 29 01:53:06 PDT 2019
Author: c-rhodes
Date: Wed May 29 01:53:06 2019
New Revision: 361935
URL: http://llvm.org/viewvc/llvm-project?rev=361935&view=rev
Log:
[AArch64][SVE2] Asm: support Floating Point Widening Multiply-Add
Summary:
Patch adds support for the indexed and unpredicated vectors forms of the
FMLALB, FMLALT, FMLSLB and FMLSLT instructions.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D62386
Added:
llvm/trunk/test/MC/AArch64/SVE2/fmlalb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE2/fmlalb.s
llvm/trunk/test/MC/AArch64/SVE2/fmlalt-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE2/fmlalt.s
llvm/trunk/test/MC/AArch64/SVE2/fmlslb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE2/fmlslb.s
llvm/trunk/test/MC/AArch64/SVE2/fmlslt-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE2/fmlslt.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
llvm/trunk/test/MC/AArch64/SVE/movprfx-diagnostics.s
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=361935&r1=361934&r2=361935&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Wed May 29 01:53:06 2019
@@ -1301,6 +1301,18 @@ let Predicates = [HasSVE2] in {
defm FMAXP_ZPmZZ : sve2_fp_pairwise_pred<0b110, "fmaxp">;
defm FMINP_ZPmZZ : sve2_fp_pairwise_pred<0b111, "fminp">;
+ // SVE2 floating-point multiply-add long (indexed)
+ def FMLALB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b00, "fmlalb">;
+ def FMLALT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b01, "fmlalt">;
+ def FMLSLB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b10, "fmlslb">;
+ def FMLSLT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b11, "fmlslt">;
+
+ // SVE2 floating-point multiply-add long
+ def FMLALB_ZZZ_SHH : sve2_fp_mla_long<0b00, "fmlalb">;
+ def FMLALT_ZZZ_SHH : sve2_fp_mla_long<0b01, "fmlalt">;
+ def FMLSLB_ZZZ_SHH : sve2_fp_mla_long<0b10, "fmlslb">;
+ def FMLSLT_ZZZ_SHH : sve2_fp_mla_long<0b11, "fmlslt">;
+
// Predicated shifts
defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=361935&r1=361934&r2=361935&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Wed May 29 01:53:06 2019
@@ -1506,6 +1506,62 @@ multiclass sve2_fp_pairwise_pred<bits<3>
}
//===----------------------------------------------------------------------===//
+// SVE2 Floating Point Widening Multiply-Add - Indexed Group
+//===----------------------------------------------------------------------===//
+
+class sve2_fp_mla_long_by_indexed_elem<bits<2> opc, string asm>
+: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm,
+ VectorIndexH:$iop),
+ asm, "\t$Zda, $Zn, $Zm$iop",
+ "",
+ []>, Sched<[]> {
+ bits<5> Zda;
+ bits<5> Zn;
+ bits<3> Zm;
+ bits<3> iop;
+ let Inst{31-21} = 0b01100100101;
+ let Inst{20-19} = iop{2-1};
+ let Inst{18-16} = Zm;
+ let Inst{15-14} = 0b01;
+ let Inst{13} = opc{1};
+ let Inst{12} = 0b0;
+ let Inst{11} = iop{0};
+ let Inst{10} = opc{0};
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zda;
+
+ let Constraints = "$Zda = $_Zda";
+ let DestructiveInstType = Destructive;
+ let ElementSize = ElementSizeNone;
+}
+
+//===----------------------------------------------------------------------===//
+// SVE2 Floating Point Widening Multiply-Add Group
+//===----------------------------------------------------------------------===//
+
+class sve2_fp_mla_long<bits<2> opc, string asm>
+: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm),
+ asm, "\t$Zda, $Zn, $Zm",
+ "",
+ []>, Sched<[]> {
+ bits<5> Zda;
+ bits<5> Zn;
+ bits<5> Zm;
+ let Inst{31-21} = 0b01100100101;
+ let Inst{20-16} = Zm;
+ let Inst{15-14} = 0b10;
+ let Inst{13} = opc{1};
+ let Inst{12-11} = 0b00;
+ let Inst{10} = opc{0};
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zda;
+
+ let Constraints = "$Zda = $_Zda";
+ let DestructiveInstType = Destructive;
+ let ElementSize = ElementSizeNone;
+}
+
+//===----------------------------------------------------------------------===//
// SVE Stack Allocation Group
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/AArch64/SVE/movprfx-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/movprfx-diagnostics.s?rev=361935&r1=361934&r2=361935&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/movprfx-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/movprfx-diagnostics.s Wed May 29 01:53:06 2019
@@ -111,6 +111,16 @@ mla z0.d, p0/m, z0.d, z2.d
// ------------------------------------------------------------------------- //
+// Destination used in other operand (ternary + indexed)
+
+movprfx z0, z1
+sdot z0.s, z1.b, z0.b[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source
+// CHECK-NEXT: sdot z0.s, z1.b, z0.b[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
// Different general predicate (unary)
movprfx z0.d, p0/m, z1.d
Added: llvm/trunk/test/MC/AArch64/SVE2/fmlalb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fmlalb-diagnostics.s?rev=361935&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fmlalb-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fmlalb-diagnostics.s Wed May 29 01:53:06 2019
@@ -0,0 +1,71 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+fmlalb z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmlalb z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+fmlalb z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalb z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fmlalb z0.s, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalb z0.s, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalb z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalb z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalb z0.s, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalb z0.s, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalb z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalb z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalb z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalb z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalb z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalb z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z29.s, p0/z, z7.s
+fmlalb z29.s, z30.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlalb z29.s, z30.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.s, p0/z, z7.s
+fmlalb z0.s, z1.h, z7.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE2/fmlalb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fmlalb.s?rev=361935&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fmlalb.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fmlalb.s Wed May 29 01:53:06 2019
@@ -0,0 +1,54 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+fmlalb z29.s, z30.h, z31.h
+// CHECK-INST: fmlalb z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0x83,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 83 bf 64 <unknown>
+
+fmlalb z0.s, z1.h, z7.h[0]
+// CHECK-INST: fmlalb z0.s, z1.h, z7.h[0]
+// CHECK-ENCODING: [0x20,0x40,0xa7,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 40 a7 64 <unknown>
+
+fmlalb z30.s, z31.h, z7.h[7]
+// CHECK-INST: fmlalb z30.s, z31.h, z7.h[7]
+// CHECK-ENCODING: [0xfe,0x4b,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: fe 4b bf 64 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z29, z28
+// CHECK-INST: movprfx z29, z28
+// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
+
+fmlalb z29.s, z30.h, z31.h
+// CHECK-INST: fmlalb z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0x83,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 83 bf 64 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+fmlalb z21.s, z1.h, z7.h[7]
+// CHECK-INST: fmlalb z21.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x35,0x48,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 48 bf 64 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE2/fmlalt-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fmlalt-diagnostics.s?rev=361935&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fmlalt-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fmlalt-diagnostics.s Wed May 29 01:53:06 2019
@@ -0,0 +1,71 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+fmlalt z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmlalt z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+fmlalt z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalt z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fmlalt z0.s, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalt z0.s, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalt z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalt z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalt z0.s, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalt z0.s, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalt z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalt z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalt z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalt z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalt z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalt z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z29.s, p0/z, z7.s
+fmlalt z29.s, z30.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlalt z29.s, z30.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.s, p0/z, z7.s
+fmlalt z0.s, z1.h, z7.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE2/fmlalt.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fmlalt.s?rev=361935&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fmlalt.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fmlalt.s Wed May 29 01:53:06 2019
@@ -0,0 +1,54 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+fmlalt z29.s, z30.h, z31.h
+// CHECK-INST: fmlalt z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0x87,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 87 bf 64 <unknown>
+
+fmlalt z0.s, z1.h, z7.h[0]
+// CHECK-INST: fmlalt z0.s, z1.h, z7.h[0]
+// CHECK-ENCODING: [0x20,0x44,0xa7,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 44 a7 64 <unknown>
+
+fmlalt z30.s, z31.h, z7.h[7]
+// CHECK-INST: fmlalt z30.s, z31.h, z7.h[7]
+// CHECK-ENCODING: [0xfe,0x4f,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: fe 4f bf 64 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z29, z28
+// CHECK-INST: movprfx z29, z28
+// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
+
+fmlalt z29.s, z30.h, z31.h
+// CHECK-INST: fmlalt z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0x87,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 87 bf 64 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+fmlalt z21.s, z1.h, z7.h[7]
+// CHECK-INST: fmlalt z21.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x35,0x4c,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 4c bf 64 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE2/fmlslb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fmlslb-diagnostics.s?rev=361935&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fmlslb-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fmlslb-diagnostics.s Wed May 29 01:53:06 2019
@@ -0,0 +1,71 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+fmlslb z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmlslb z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+fmlslb z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslb z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fmlslb z0.s, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslb z0.s, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslb z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslb z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslb z0.s, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslb z0.s, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslb z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslb z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslb z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslb z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslb z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslb z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z29.s, p0/z, z7.s
+fmlslb z29.s, z30.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlslb z29.s, z30.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.s, p0/z, z7.s
+fmlslb z0.s, z1.h, z7.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE2/fmlslb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fmlslb.s?rev=361935&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fmlslb.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fmlslb.s Wed May 29 01:53:06 2019
@@ -0,0 +1,54 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+fmlslb z29.s, z30.h, z31.h
+// CHECK-INST: fmlslb z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd a3 bf 64 <unknown>
+
+fmlslb z0.s, z1.h, z7.h[0]
+// CHECK-INST: fmlslb z0.s, z1.h, z7.h[0]
+// CHECK-ENCODING: [0x20,0x60,0xa7,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 60 a7 64 <unknown>
+
+fmlslb z30.s, z31.h, z7.h[7]
+// CHECK-INST: fmlslb z30.s, z31.h, z7.h[7]
+// CHECK-ENCODING: [0xfe,0x6b,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: fe 6b bf 64 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z29, z28
+// CHECK-INST: movprfx z29, z28
+// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
+
+fmlslb z29.s, z30.h, z31.h
+// CHECK-INST: fmlslb z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd a3 bf 64 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+fmlslb z21.s, z1.h, z7.h[7]
+// CHECK-INST: fmlslb z21.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x35,0x68,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 68 bf 64 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE2/fmlslt-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fmlslt-diagnostics.s?rev=361935&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fmlslt-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fmlslt-diagnostics.s Wed May 29 01:53:06 2019
@@ -0,0 +1,71 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+fmlslt z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmlslt z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+fmlslt z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslt z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fmlslt z0.s, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslt z0.s, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslt z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslt z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslt z0.s, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslt z0.s, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslt z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslt z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslt z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslt z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslt z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslt z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z29.s, p0/z, z7.s
+fmlslt z29.s, z30.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlslt z29.s, z30.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.s, p0/z, z7.s
+fmlslt z0.s, z1.h, z7.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE2/fmlslt.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fmlslt.s?rev=361935&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fmlslt.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fmlslt.s Wed May 29 01:53:06 2019
@@ -0,0 +1,54 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+fmlslt z29.s, z30.h, z31.h
+// CHECK-INST: fmlslt z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd a7 bf 64 <unknown>
+
+fmlslt z0.s, z1.h, z7.h[0]
+// CHECK-INST: fmlslt z0.s, z1.h, z7.h[0]
+// CHECK-ENCODING: [0x20,0x64,0xa7,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 64 a7 64 <unknown>
+
+fmlslt z30.s, z31.h, z7.h[7]
+// CHECK-INST: fmlslt z30.s, z31.h, z7.h[7]
+// CHECK-ENCODING: [0xfe,0x6f,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: fe 6f bf 64 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z29, z28
+// CHECK-INST: movprfx z29, z28
+// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
+
+fmlslt z29.s, z30.h, z31.h
+// CHECK-INST: fmlslt z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd a7 bf 64 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+fmlslt z21.s, z1.h, z7.h[7]
+// CHECK-INST: fmlslt z21.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x35,0x6c,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 6c bf 64 <unknown>
More information about the llvm-commits
mailing list