[llvm] r361877 - [AArch64] Handle ISD::LRINT and ISD::LLRINT
Adhemerval Zanella via llvm-commits
llvm-commits at lists.llvm.org
Tue May 28 14:04:30 PDT 2019
Author: azanella
Date: Tue May 28 14:04:29 2019
New Revision: 361877
URL: http://llvm.org/viewvc/llvm-project?rev=361877&view=rev
Log:
[AArch64] Handle ISD::LRINT and ISD::LLRINT
This patch optimizes ISD::LRINT and ISD::LLRINT to frintx plus
fcvtzs. It currently only handles the scalar version.
Reviewed By: SjoerdMeijer, mstorsjo
Differential Revision: https://reviews.llvm.org/D62018
Added:
llvm/trunk/test/CodeGen/AArch64/lrint-conv-win.ll
Modified:
llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
llvm/trunk/test/CodeGen/AArch64/llrint-conv.ll
llvm/trunk/test/CodeGen/AArch64/lrint-conv.ll
Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=361877&r1=361876&r2=361877&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Tue May 28 14:04:29 2019
@@ -453,6 +453,8 @@ def fround : SDNode<"ISD::FROUND"
def lround : SDNode<"ISD::LROUND" , SDTFPToIntOp>;
def llround : SDNode<"ISD::LLROUND" , SDTFPToIntOp>;
+def lrint : SDNode<"ISD::LRINT" , SDTFPToIntOp>;
+def llrint : SDNode<"ISD::LLRINT" , SDTFPToIntOp>;
def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=361877&r1=361876&r2=361877&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue May 28 14:04:29 2019
@@ -459,6 +459,8 @@ AArch64TargetLowering::AArch64TargetLowe
setOperationAction(ISD::FMAXIMUM, Ty, Legal);
setOperationAction(ISD::LROUND, Ty, Legal);
setOperationAction(ISD::LLROUND, Ty, Legal);
+ setOperationAction(ISD::LRINT, Ty, Legal);
+ setOperationAction(ISD::LLRINT, Ty, Legal);
}
if (Subtarget->hasFullFP16()) {
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=361877&r1=361876&r2=361877&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Tue May 28 14:04:29 2019
@@ -3160,6 +3160,19 @@ let Predicates = [HasFRInt3264] in {
defm FRINT64X : FRIntNNT<0b11, "frint64x">;
} // HasFRInt3264
+def : Pat<(i32 (lrint f32:$Rn)),
+ (FCVTZSUWSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
+def : Pat<(i32 (lrint f64:$Rn)),
+ (FCVTZSUWDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
+def : Pat<(i64 (lrint f32:$Rn)),
+ (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
+def : Pat<(i64 (lrint f64:$Rn)),
+ (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
+def : Pat<(i64 (llrint f32:$Rn)),
+ (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
+def : Pat<(i64 (llrint f64:$Rn)),
+ (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
+
//===----------------------------------------------------------------------===//
// Floating point two operand instructions.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/CodeGen/AArch64/llrint-conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/llrint-conv.ll?rev=361877&r1=361876&r2=361877&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/llrint-conv.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/llrint-conv.ll Tue May 28 14:04:29 2019
@@ -1,7 +1,9 @@
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
; CHECK-LABEL: testmsws:
-; CHECK: bl llrintf
+; CHECK: frintx [[REG:s[0-9]]], s0
+; CHECK-NEXT: fcvtzs x0, [[REG]]
+; CHECK: ret
define i32 @testmsws(float %x) {
entry:
%0 = tail call i64 @llvm.llrint.f32(float %x)
@@ -10,7 +12,9 @@ entry:
}
; CHECK-LABEL: testmsxs:
-; CHECK: b llrintf
+; CHECK: frintx [[REG:s[0-9]]], s0
+; CHECK-NEXT: fcvtzs x0, [[REG]]
+; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i64 @llvm.llrint.f32(float %x)
@@ -18,7 +22,9 @@ entry:
}
; CHECK-LABEL: testmswd:
-; CHECK: bl llrint
+; CHECK: frintx [[REG:d[0-9]]], d0
+; CHECK-NEXT: fcvtzs x0, [[REG]]
+; CHECK: ret
define i32 @testmswd(double %x) {
entry:
%0 = tail call i64 @llvm.llrint.f64(double %x)
@@ -27,7 +33,9 @@ entry:
}
; CHECK-LABEL: testmsxd:
-; CHECK: b llrint
+; CHECK: frintx [[REG:d[0-9]]], d0
+; CHECK-NEXT: fcvtzs x0, [[REG]]
+; CHECK-nEXT: ret
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i64 @llvm.llrint.f64(double %x)
Added: llvm/trunk/test/CodeGen/AArch64/lrint-conv-win.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/lrint-conv-win.ll?rev=361877&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/lrint-conv-win.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/lrint-conv-win.ll Tue May 28 14:04:29 2019
@@ -0,0 +1,48 @@
+; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
+
+; CHECK-LABEL: testmsxs:
+; CHECK: frintx [[SREG:s[0-9]+]], s0
+; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]]
+; CHECK-NEXT: sxtw x0, [[WREG]]
+; CHECK-NEXT: ret
+define i64 @testmsxs(float %x) {
+entry:
+ %0 = tail call i32 @llvm.lrint.i32.f32(float %x)
+ %conv = sext i32 %0 to i64
+ ret i64 %conv
+}
+
+; CHECK-LABEL: testmsws:
+; CHECK: frintx [[SREG:s[0-9]+]], s0
+; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]]
+; CHECK-NEXT: ret
+define i32 @testmsws(float %x) {
+entry:
+ %0 = tail call i32 @llvm.lrint.i32.f32(float %x)
+ ret i32 %0
+}
+
+; CHECK-LABEL: testmsxd:
+; CHECK: frintx [[DREG:d[0-9]+]], d0
+; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]]
+; CHECK-NEXT: sxtw x0, [[WREG]]
+; CHECK-NEXT: ret
+define i64 @testmsxd(double %x) {
+entry:
+ %0 = tail call i32 @llvm.lrint.i32.f64(double %x)
+ %conv = sext i32 %0 to i64
+ ret i64 %conv
+}
+
+; CHECK-LABEL: testmswd:
+; CHECK: frintx [[DREG:d[0-9]+]], d0
+; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]]
+; CHECK-NEXT: ret
+define i32 @testmswd(double %x) {
+entry:
+ %0 = tail call i32 @llvm.lrint.i32.f64(double %x)
+ ret i32 %0
+}
+
+declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
+declare i32 @llvm.lrint.i32.f64(double) nounwind readnone
Modified: llvm/trunk/test/CodeGen/AArch64/lrint-conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/lrint-conv.ll?rev=361877&r1=361876&r2=361877&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/lrint-conv.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/lrint-conv.ll Tue May 28 14:04:29 2019
@@ -1,7 +1,9 @@
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
; CHECK-LABEL: testmsws:
-; CHECK: bl lrintf
+; CHECK: frintx [[REG:s[0-9]]], s0
+; CHECK-NEXT: fcvtzs x0, [[REG]]
+; CHECK: ret
define i32 @testmsws(float %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f32(float %x)
@@ -10,7 +12,9 @@ entry:
}
; CHECK-LABEL: testmsxs:
-; CHECK: b lrintf
+; CHECK: frintx [[REG:s[0-9]]], s0
+; CHECK-NEXT: fcvtzs x0, [[REG]]
+; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f32(float %x)
@@ -18,7 +22,9 @@ entry:
}
; CHECK-LABEL: testmswd:
-; CHECK: bl lrint
+; CHECK: frintx [[REG:d[0-9]]], d0
+; CHECK-NEXT: fcvtzs x0, [[REG]]
+; CHECK: ret
define i32 @testmswd(double %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f64(double %x)
@@ -27,7 +33,9 @@ entry:
}
; CHECK-LABEL: testmsxd:
-; CHECK: b lrint
+; CHECK: frintx [[REG:d[0-9]]], d0
+; CHECK-NEXT: fcvtzs x0, [[REG]]
+; CHECK-NEXT: ret
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f64(double %x)
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