[PATCH] D62543: [MIR-Canon] Add support for rewriting VRegs that are typed but don't have an RC.

[Puyan Lotfi via Phabricator via llvm-commits]

plotfi created this revision.
Herald added subscribers: llvm-commits, hiraditya, javed.absar.
Herald added a project: LLVM.

So it appears that in a lot of cases before registerbanks are selected, we dont have Register classes and MIR-Canon is crashing. This attempts to fix this by creating new override registers that use the generic type rather than the register class.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D62543

Files:
  llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
  llvm/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir


Index: llvm/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir
===================================================================
--- llvm/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir
+++ llvm/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass mir-canonicalizer -o - %s
 
 --- |
 
Index: llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
===================================================================
--- llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
+++ llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
@@ -317,6 +317,15 @@
   return Changed;
 }
 
+static bool doVRegTypesMatch(const MachineRegisterInfo &MRI, unsigned VReg0,
+                             unsigned VReg1) {
+  if (MRI.getRegClassOrNull(VReg0) == MRI.getRegClassOrNull(VReg1))
+    return MRI.getRegClassOrNull(VReg0) != nullptr
+               ? true
+               : MRI.getType(VReg0) == MRI.getType(VReg1);
+  return false;
+}
+
 static bool propagateLocalCopies(MachineBasicBlock *MBB) {
   bool Changed = false;
   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
@@ -341,7 +350,7 @@
       continue;
     if (!TargetRegisterInfo::isVirtualRegister(Src))
       continue;
-    if (MRI.getRegClass(Dst) != MRI.getRegClass(Src))
+    if (!doVRegTypesMatch(MRI, Dst, Src))
       continue;
 
     for (auto UI = MRI.use_begin(Dst); UI != MRI.use_end(); ++UI) {
@@ -500,14 +509,16 @@
     return virtualVRegNumber;
   }
 
-  unsigned createVirtualRegister(const TargetRegisterClass *RC) {
+  unsigned createVirtualRegister(MachineRegisterInfo &MRI, unsigned VReg) {
+    auto RC = MRI.getRegClassOrNull(VReg);
     std::string S;
     raw_string_ostream OS(S);
     OS << "namedVReg" << (virtualVRegNumber & ~0x80000000);
     OS.flush();
     virtualVRegNumber++;
-
-    return MRI.createVirtualRegister(RC, OS.str());
+    if (RC)
+      return MRI.createVirtualRegister(RC, OS.str());
+    return MRI.createGenericVirtualRegister(MRI.getType(VReg), OS.str());
   }
 };
 } // namespace
@@ -557,7 +568,7 @@
       continue;
     }
 
-    auto Rename = NVC.createVirtualRegister(MRI.getRegClass(Reg));
+    auto Rename = NVC.createVirtualRegister(MRI, Reg);
 
     if (VRegRenameMap.find(Reg) == VRegRenameMap.end()) {
       LLVM_DEBUG(dbgs() << "Mapping vreg ";);
@@ -741,7 +752,7 @@
     MachineInstr &MI = *MII++;
     Changed = true;
     unsigned vRegToRename = MI.getOperand(0).getReg();
-    auto Rename = NVC.createVirtualRegister(MRI.getRegClass(vRegToRename));
+    auto Rename = NVC.createVirtualRegister(MRI, vRegToRename);
 
     std::vector<MachineOperand *> RenameMOs;
     for (auto &MO : MRI.reg_operands(vRegToRename)) {


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