[llvm] r361796 - [AArch64][SVE2] Asm: support SVE2 Histogram Computation Groups
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Tue May 28 01:51:59 PDT 2019
Author: c-rhodes
Date: Tue May 28 01:51:59 2019
New Revision: 361796
URL: http://llvm.org/viewvc/llvm-project?rev=361796&view=rev
Log:
[AArch64][SVE2] Asm: support SVE2 Histogram Computation Groups
Summary:
Patch adds support for the following instructions:
SVE2 histogram generation (segment):
* HISTSEG
SVE2 histogram generation (vector):
* HISTCNT
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D62306
Added:
llvm/trunk/test/MC/AArch64/SVE2/histcnt-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE2/histcnt.s
llvm/trunk/test/MC/AArch64/SVE2/histseg-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE2/histseg.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=361796&r1=361795&r2=361796&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Tue May 28 01:51:59 2019
@@ -1283,6 +1283,12 @@ let Predicates = [HasSVE2] in {
defm SSUBLBT_ZZZ : sve2_misc_int_addsub_long_interleaved<0b10, "ssublbt">;
defm SSUBLTB_ZZZ : sve2_misc_int_addsub_long_interleaved<0b11, "ssubltb">;
+ // SVE2 histogram generation (segment)
+ def HISTSEG_ZZZ : sve2_hist_gen_segment<"histseg">;
+
+ // SVE2 histogram generation (vector)
+ defm HISTCNT_ZPzZZ : sve2_hist_gen_vector<"histcnt">;
+
// Predicated shifts
defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=361796&r1=361795&r2=361796&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Tue May 28 01:51:59 2019
@@ -5239,3 +5239,50 @@ multiclass sve2_char_match<bit opc, stri
def _B : sve2_char_match<0b0, opc, asm, PPR8, ZPR8>;
def _H : sve2_char_match<0b1, opc, asm, PPR16, ZPR16>;
}
+
+//===----------------------------------------------------------------------===//
+// SVE2 Histogram Computation - Segment Group
+//===----------------------------------------------------------------------===//
+
+class sve2_hist_gen_segment<string asm>
+: I<(outs ZPR8:$Zd), (ins ZPR8:$Zn, ZPR8:$Zm),
+ asm, "\t$Zd, $Zn, $Zm",
+ "",
+ []>, Sched<[]> {
+ bits<5> Zd;
+ bits<5> Zn;
+ bits<5> Zm;
+ let Inst{31-21} = 0b01000101001;
+ let Inst{20-16} = Zm;
+ let Inst{15-10} = 0b101000;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zd;
+}
+
+//===----------------------------------------------------------------------===//
+// SVE2 Histogram Computation - Vector Group
+//===----------------------------------------------------------------------===//
+
+class sve2_hist_gen_vector<bit sz, string asm, ZPRRegOp zprty>
+: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
+ asm, "\t$Zd, $Pg/z, $Zn, $Zm",
+ "",
+ []>, Sched<[]> {
+ bits<5> Zd;
+ bits<5> Zn;
+ bits<3> Pg;
+ bits<5> Zm;
+ let Inst{31-23} = 0b010001011;
+ let Inst{22} = sz;
+ let Inst{21} = 0b1;
+ let Inst{20-16} = Zm;
+ let Inst{15-13} = 0b110;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zd;
+}
+
+multiclass sve2_hist_gen_vector<string asm> {
+ def _S : sve2_hist_gen_vector<0b0, asm, ZPR32>;
+ def _D : sve2_hist_gen_vector<0b1, asm, ZPR64>;
+}
Added: llvm/trunk/test/MC/AArch64/SVE2/histcnt-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/histcnt-diagnostics.s?rev=361796&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/histcnt-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/histcnt-diagnostics.s Tue May 28 01:51:59 2019
@@ -0,0 +1,49 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Invalid element width
+
+histcnt z0.b, p0/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: histcnt z0.b, p0/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+histcnt z0.h, p0/z, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: histcnt z0.h, p0/z, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+histcnt z0.s, p0/m, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: histcnt z0.s, p0/m, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate not in restricted predicate range
+
+histcnt z0.s, p8/z, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: histcnt z0.s, p8/z, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.s, p0/z, z7.s
+histcnt z0.s, p7/z, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: histcnt z0.s, p7/z, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0, z7
+histcnt z0.s, p7/z, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: histcnt z0.s, p7/z, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE2/histcnt.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/histcnt.s?rev=361796&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/histcnt.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/histcnt.s Tue May 28 01:51:59 2019
@@ -0,0 +1,21 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+histcnt z0.s, p0/z, z1.s, z2.s
+// CHECK-INST: histcnt z0.s, p0/z, z1.s, z2.s
+// CHECK-ENCODING: [0x20,0xc0,0xa2,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 c0 a2 45 <unknown>
+
+histcnt z29.d, p7/z, z30.d, z31.d
+// CHECK-INST: histcnt z29.d, p7/z, z30.d, z31.d
+// CHECK-ENCODING: [0xdd,0xdf,0xff,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd df ff 45 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE2/histseg-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/histseg-diagnostics.s?rev=361796&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/histseg-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/histseg-diagnostics.s Tue May 28 01:51:59 2019
@@ -0,0 +1,36 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Invalid element width
+
+histseg z0.h, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: histseg z0.h, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+histseg z0.s, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: histseg z0.s, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+histseg z0.d, z0.d, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: histseg z0.d, z0.d, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z31, z6
+histseg z31.b, z30.b, z29.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: histseg z31.b, z30.b, z29.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z31.b, p0/m, z6.b
+histseg z31.b, z30.b, z29.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: histseg z31.b, z30.b, z29.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE2/histseg.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/histseg.s?rev=361796&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/histseg.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/histseg.s Tue May 28 01:51:59 2019
@@ -0,0 +1,15 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+histseg z0.b, z1.b, z31.b
+// CHECK-INST: histseg z0.b, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0xa0,0x3f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 a0 3f 45 <unknown>
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